Read-only memory and read-only memory devices

Details Read-only memory and read-only memory devices Read-only memory and read-only memory devices

1999-09-13

2001-05-22

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read only systems

Semiconductive

C365S100000

Reexamination Certificate

active

06236587

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention concerns an electrically addressable, non-volatile read-only memory, comprising a plurality of memory cells which in a write operation comprising a part of the manufacturing process of the read-only memory, permanently each are assigned one or two or more logic states according to a determined protocol which in the memory defines permanently written or stored data, and a passive matrix of electrical conductors for the addressing, wherein the passive electrical conductor matrix comprises a first and a second electrode structure in respective mutually spaced apart and parallel planes and with parallel electrodes in each plane and provided such that the electrodes form a substantially orthogonal x,y matrix wherein the electrodes in the first electrode structure comprise the columns of the matrix or x electrodes and the electrodes in the second electrode structure comprise the rows of the matrix or y electrodes, wherein at least a portion of the volume between the intersection of an x electrode and a y electrode defines a memory cell in the read-only memory, wherein a contact area in the memory cell is defined by the portions which respectively extend along each side edge of the y electrode where it overlaps the x electrode in the memory cell, wherein are provided at least one semiconductor material with rectifying properties in relation to a selected electrical conducting electrode material, and a first electrical isolating material, and wherein the semiconductor material in electrical contact with an electrode in the memory cell forms a diode junction in the interface between semiconductor material and electrode material.
The invention also concerns a read-only memory device which comprises one or more read-only memories according to the invention, and a read-only memory device which comprises two or more read-only memories according to the invention.
FIELD OF THE INVENTION
Matrix addressing of data storage locations or bit spots on a plane is a simple and efficient way of achieving a great number of accessible memory locations with a moderate number of electrical addressing lines. In a square x,y matrix with n lines respectively both in the x direction and the y direction the number of memory locations scales as n
2
. In one form or another this basic principle is at present implemented in a large number of different embodiments of solid state memory means. In these the memory location comprises a simple electronic circuit which communicates to the outside via the intersection in the matrix and a memory element, typically a charge storage device. Even if such means have been technically and commercially very successful, they have a number of disadvantages, and particularly each memory location has a complex architecture which leads to increased costs and reduced data storage density. In the large subclass of so-called volatile memory means the circuits must constantly sustain a current supply with accompanying heating and consumption of electric power in order to maintain the stored information. On the other hand non-volatile means avoid this problem, but with the trade-off of a reduced access and switching time as well as increased consumption and high complexity.
Prior art provides a number of examples of semiconductor-based read-only memories with electrical addressing in passive matrix. Thus U.S. Pat. No. 4,099,260 (Lynes et al.) discloses a semiconductor-based read-only memory (ROM) made as a large scale integrated device wherein self-isolating bit line surface areas of one conduction type are formed in a semiconductor substrate and directly in a bulk area in the opposite conduction type. Channel stop areas of the same conduction type as the bulk area are formed in the intervals between the bit line areas. Metallic word lines which lie above and are orthogonal to the bit line areas are formed separately from these by means of an isolating layer. The memory cell comprises a single Schottky diode. A diode of this kind will be formed or not at each intersection between a word line and a bit line depending on whether or not an opening is formed in the isolating layer during manufacturing in order to permit the word line to contact a lightly doped portion of the bit line. A ROM of this kind is stated to have a small area, high speed, low power dissipation and low cost.
Further there are from U.S. Pat. No. 4,000,713 (Bauge & Mollier) known a device with semiconductor elements, such as Schottky diodes and transistors integrated in the form of a matrix on chips. The matrix may be custom designed in order to provide a desired function. For instance it may be used as AND or OR matrices in programmable logic arrays (PLA) or as read-only memories which are stated to have better properties with regard to storage density and power dissipation. A first electrode structure with parallel metal electrodes of somewhat different design is provided on a semiconductor substrate of for instance the p type. An oxide layer is provided on a semiconductor substrate and openings are formed in the oxide layer to provide anode contacts and cathode contacts via metallic lines which constitute a first metal level in the electrode matrix. Two n
−
areas are located under the cathode contacts. These areas extend to underlying collector layers such that a Schottky diode is formed. Above the first metal level or electrode level an isolating layer is provided and over this a second metal level which comprises for instance an orthogonal second electrode structure. Openings through the isolating layer ensure contact with a cathode contact in a group of such which are included in the separate element in the matrix.
Finally there are from U.S. Pat. No. 5,272,370 (French) known a thin-film ROM device based on a matrix of open and closed memory cells formed in a stack of thin films on glass or another substrate. Each closed memory cell comprises a thin-film diode and it may by using stacks of semiconductor films, for instance of hydrogenated amorphous silicon, wherein the separate films are of different conduction types, be obtained diodes with different conduction characteristics. Thereby the information content in the ROM matrix may be increased. Each memory element which is formed with diode structure may then be set with different logic levels according to some manufacturing protocol. Where the memory element does not have a diode structure or where the semiconductors are covered by an isolating layer such that no electrode contact is formed, the memory element may be used to form a determined first logic level, for instance logical 0.
Even though the above-mentioned prior-art devices all realize electrical addressing in passive matrix in an as per se known manner by providing diode junctions in closed electrode contacts, they have partly due to using different types of semiconductors a relatively high degree of complexity. In the ROM device as disclosed in the last-mentioned publication (U.S. Pat. No. 5,272,370) it may, however, be possible to store more than two logical values in the matrix, but this presupposes use of different diode types and hence several layers of differently doped semiconductors in the bit spot with diode junction.
The object of the present invention is hence primarily to provide a read-only memory or ROM which permits electrical addressing in passive matrix to the separate memory cell in the read-only memory and which does not need refreshment in order to keep the data stored in the memory cell, while the read-only memory shall be simply and cheaply realized using as per se known technologies and methods as applied in the semiconductor and thin-film technology.
Particularly it is the object of the present invention to provide a non-volatile read-only memory based on the use of organic materials, for instance polymer materials, which realized in thin-film technology may be used both in conductors, isolators and semiconductor materials, something which supposedly shall provide more flexible technical solutions and especially a much

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