Read only memory

Details Read only memory Read only memory

1998-05-21

2001-05-01

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S104000

Reexamination Certificate

active

06226214

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to read only memories (ROMs), and more specifically to NOR-type ROMs.
BACKGROUND OF THE INVENTION
There has been widely used, as a ROM (or mask ROM), the NOR-type ROM in which sources and drains of memory cells are formed with N-type conductive diffusion regions and word lines are arranged perpendicular to the diffusion regions. A circuit pattern with a matrix of memory cells in the N-type diffusion layers has been proposed in U.S. Pat. No. 5,268,861 by Y. Hotta et al and U.S. Pat. No. 5,349,563 by T. Iwase.
FIG. 1
shows Hotta's circuit configuration of a memory cell array in a ROM, and
FIG. 2
is a plan view of the same memory cell array. In
FIG. 1
, the arrangement of bit lines is constructed of main bit lines MBL
1
~MBL
4
and sub-bit lines SB
1
~SB
8
. Each of the odd-numbered main bit lines are connected to two of the odd-numbered sub-bit lines through two of the odd-numbered bank selection transistors BSO
1
~BSO
4
in which gates of BSO
1
and BSO
3
are coupled to bank selection line BO
1
and gates of BSO
2
and BSO
4
to BO
2
. Each of the even-numbered main bit lines are connected to two of the even-numbered sub-bit lines through two of even-numbered bank selection transistors BSE
1
~BSE
4
in which gates of BSE
1
and BSE
3
are coupled to bank selection line BE
1
and gates of BSE
2
and BSE
4
to BE
2
. And the odd-numbered main bit lines MBL
1
and MBL
3
are each coupled to sense amplifiers SA
1
and SA
2
, and the even-numbered main bit lines MBL
2
and MBL
2
are connected to a ground potential each through transistors Q
2
and Q
3
gates of which are connected to control signal VS. Each of word lines WL
1
~WLn intersecting the bit lines is coupled to control gates of memory cells that are arranged in a row direction, while each of the sub-bit lines is coupled to adjacent memory cells.
In a read operation, assuming that M
41
is on-cell and selected therein, BO
1
and BE
2
are set into a high potential while BO
2
and BE
1
are held in a low potential. WL
1
goes to high level and VS is too high to switch Q
2
on. Therefore, the current path for sensing is formed from MBL to the ground, through BSO
3
, SB
5
, M
41
, SB
4
, BSE
2
, MBL
2
and Q
2
.
Referring
FIG. 2
, it is well known that the current path for sensing includes two regions
3
and
4
which are vertically formed of the diffusion layer, a gate oxide layer and the word line, as well as passing through the aforementioned positions. Such constructions of stray capacitances involved in the sensing current path cause the level of the sensing voltage to be reduced thereby, resulting in degrading an efficiency of the sensing operation. On the other hand, the sub-bit lines are formed by an N-conductive type diffusion layer, which is used for an active region of the bank selection transistor and determines channel width W of the bank selection transistor as shown in FIG.
2
. The limit against the channel width of the bank selection transistor causes an increase of on-resistance (a resistance when the sensing current flows through an on cell) that reduces the amount of the sensing current for the on-cell.
Furthermore, the main bit line is connected to the active region of the bank selection transistor, at region
1
of the diffusion layer, through contact hole
2
. With this construction, a junction capacitance between the main bit line and the region
2
and a gate capacitance of the bank selection transistor at the bit line badly influences the speed of data accessing.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the invention to provide a ROM capable of enhancing the speed of data sensing.
It is another object of the invention to provide a ROM capable of reducing resistance and capacitance during a read operation.
Typically, in order to accomplish those objects, a memory of this invention, having a plurality of memory blocks each associated with main bit lines and sub-bit lines, and a plurality of memory cells for storing information, and sense amplifiers for reading the information stored in the memory cells through the main bit lines, includes a block selection part disposed between the blocks and having a plurality of block selection transistors connecting the main bit lines to the sub-bit lines. The sub-bit lines elongate to at least an adjacent block and alternatively connected to the main bit lines through the block selection part and each of the block selection parts is commonly used by the adjacent blocks.
The invention specifies various aspects of the embodiment, providing a read only memory having a plurality of main bit lines and sub-bit lines including: a substrate in which a plurality of blocks are defined, each of the blocks having a plurality of memory cells storing information; a plurality of diffusion layers formed in the substrate to be used for the sub-bit lines and arranged in a row direction, the diffusion layers belong to one of the blocks being elongated to adjacent blocks; a plurality of block selection lines of conductive layers arranged in a column direction and formed over the diffusion layers in an intersectional pattern, the selection lines connected to block selection transistors formed in a selection part shared by the adjacent blocks; and a plurality of conductive layers formed over the block selection lines to be used for the main bit lines and selectively connected to the sub-bit lines through the block selection transistors, or a read only memory a read only memory having a plurality of main bit lines and sub-bit lines including: a substrate in which a plurality of blocks are defined, each of the blocks having a plurality of memory cells storing information; a plurality of diffusion layers formed in the substrate to be used for the sub-bit lines and arranged in a row direction, the diffusion layers belong to one of the blocks being elongated to an adjacent block; a plurality of first block selection lines of conductive layers arranged in a column direction and formed over the diffusion layers in an intersectional pattern, the first block selection lines connected to first block selection transistors formed in a first selection part, the first block selection transistors being formed in a diffused region and defined by field oxide regions; a plurality of second block selection lines of conductive layers arranged in the column direction and formed over the diffusion layers in an intersectional pattern, the second block selection lines connected to second block selection transistors formed in a second selection part shared by the adjacent block; and a plurality of conductive layers formed over the block selection lines to be used for the main bit lines and selectively connected to the sub-bit lines through the block selection transistors. one of the diffusion layers is electrically disconnected from another diffusion layer through a programmed region. The first block selection transistor is associated with a depletion transistor in the diffused region when a read operation is being conductive for reading information from a selected memory cell of one of the blocks.


REFERENCES:
patent: 5268861 (1993-12-01), Hotta
patent: 5349563 (1994-09-01), Iwase
patent: 5506813 (1996-04-01), Mochizuki et al.

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