Read-leveling implementations for DDR3 applications on an FPGA

Details Read-leveling implementations for DDR3 applications on an FPGA Read-leveling implementations for DDR3 applications on an FPGA

2011-08-02

2011-08-02

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S193000

Reexamination Certificate

active

07990786

ABSTRACT:
Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.

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