Read latency control circuit

Details Read latency control circuit Read latency control circuit

2008-07-22

2008-07-22

Chen, Alan S. (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C711S100000, C711S104000

Reexamination Certificate

active

07404018

ABSTRACT:
The invention provides a method for setting and controlling a read latency (L) by means of a FIFO-based read latency control circuit for a read access to a semiconductor memory, having the method steps of providing a common internal clock signal; generating an internal first clock signal and an internal second clock signal, which is different from the first clock signal, from the common clock signal; generating an output pointer for reading out the read data from the first clock signal; generating an input pointer for reading in the read data from the second clock signal; initializing the input and output pointers by allocating a defined, fixedly predetermined time offset between output pointer and input pointer. The invention furthermore provides a corresponding circuit arrangement for carrying out the method.

REFERENCES:
patent: 7260688 (2007-08-01), Baxter et al.
patent: 2005/0050375 (2005-03-01), Novak et al.
Ho Young Song et al. (2003) “A 1.2 Gb/s/pin Double Data Rate SDRAM with On-Die-Termination,” IEEE International Solid-State Circuits Conference, Session 17, Paper 17.8, 10 pages.

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