Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2003-04-08
2003-10-28
Verbrugge, Kevin (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S146000, C711S124000
Reexamination Certificate
active
06640288
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the field of caches and, more particularly, to the handling of stores to shared cache lines.
2. Description of the Related Art
A bus is frequently used in systems to interconnect a variety of devices included in the system. Generally, one or more devices are connected to the bus, and use the bus to communicate with other devices connected to the bus. Other systems may use other types of interconnect (e.g. distributed packet-based interfaces, etc.) for communicating between devices. As used herein, the term “agent” refers to a device which is capable of communicating on an interface. The agent may be a requesting agent if the agent is capable of initiating transactions on the interface and may be a responding agent if the agent is capable of responding to a transaction initiated by a requesting agent. A given agent may be capable of being both a requesting agent and a responding agent. Additionally, a “transaction” is a communication on the interface. The transaction may include an address transfer and optionally a data transfer. Transactions may be read transactions (transfers of data from the responding agent to the requesting agent) and write transactions (transfers of data from the requesting agent to the responding agent). Transactions may further include various coherency commands which may or may not involve a transfer of data.
Frequently, transactions are initiated by agents to access memory. Since agents ay cache data accessed from memory (to decrease the latency of subsequent accesses to the data), a coherency scheme may be used to ensure that the various copies of data in caches and the copy in memory remain consistent in view of updates to the data. Generally, each block in the cache may have a coherency state associated with it. The coherency state is an indication of the state of the block with respect to the corresponding data in main memory, as well as an indication of whether or not other copies are stored in other caches within the system. A variety of coherency schemes exist, many of which may include a shared coherency state. For example, the popular MESI (Modified, Exclusive, Shared, Invalid) and MOESI (Modified, Owned, Exclusive, Shared, Invalid) schemes (and various simplified forms thereof) include a shared state. The shared state indicates that the corresponding block is valid and may by cached in at least one other cache.
When an agent attempts to write a block for which the coherency state is shared (a “shared cache block” or a “shared block” herein), the other cached blocks are typically invalidated to ensure that data which does not reflect the write is not subsequently used by any agent. There are several ways to accomplish the invalidation. On some interfaces, is an explicit invalidate command is used. Receivers of the invalidate command invalidate the block indicated by the address included in the invalidate command. Unfortunately, this solution requires a command encoding on the interface to be dedicated to the invalidate command, utilizing an encoding which could be used for some other transaction type and requiring logic in the receiver of the invalidate command to decode the command and take appropriate action. Another solution is to invalidate the block in the agent attempting to write the block and then for the agent to read the block with a read exclusive command. The read exclusive command causes other copies of the block to be invalidated and the block is returned to the agent in a data phase of the read exclusive command. Unfortunately, this solution may increase the latency of the write, since the data must be returned on the interface before the write can be completed. Furthermore, the data phase may be delayed due to competition for interface bandwidth (e.g. with the data phases of earlier transactions) or due to competition for memory bandwidth to read the data block from memory.
SUMMARY OF THE INVENTION
An agent is described which, in response to a write to a shared block, is configured to initiate a read exclusive transaction on an interface on which the agent communicates. Additionally, the agent is configured to indicate, to a responding agent or agents on the interface, that a data transfer is not required from the responding agent or agents in response to the read exclusive transaction. In one embodiment, a separate encoding/logic for an invalidate transaction may be avoided, as may the complexities of handling invalidate transactions for writes to shared blocks (e.g. the underlying block to being invalidated and thus having to change the invalidate transaction to another type of transaction). Additionally, latency related to the responding agent or agents (e.g. memory controllers, L
2
caches, etc.) may not affect completion of the write to the shared block, in one embodiment.
In one embodiment, the agent indicates to the responding agents that a data transfer is not required in a response phase of the transaction. Specifically, the agent may respond in such a way that the agent indicates that it will provide the data (i.e. that the agent will provide the data to itself). For example, the agent may respond with an exclusive ownership indication. On the interface for such an embodiment, an exclusive ownership response may require that the agent having exclusive access respond with the data.
Broadly speaking, an agent is contemplated. The agent comprises a cache and an interface circuit. The cache is configured to store at least a first cache block and a first coherency state corresponding to the first cache block. The interface circuit is configured to communicate on an interface with other agents, wherein the interface circuit is configured to initiate a read exclusive transaction on the interface in response to a write which hits the first cache block and the first coherency state is shared. The interface circuit is configured, during the read exclusive transaction, to indicate to one or more responding agents of the read exclusive transaction that a data transfer is not required for the read exclusive transaction.
Additionally, a method is contemplated. A write hit to a first cache block is detected in a cache within first agent. A first coherency state corresponding to the first cache block is shared. A read exclusive transaction is initiated on an interface from the first agent in response to the detecting. During the read exclusive transaction, an indication is provided to one or more responding agents of the transaction that a data transfer is not required for the read exclusive transaction.
Moreover, an agent is contemplated. The agent comprises a cache configured to store at least a first cache block and a first coherency state corresponding to the first cache block, and an interface circuit. The interface circuit is configured to communicate on an interface with other agents, and is configured to initiate a read exclusive transaction on the interface in response to a write which hits the first cache block and the first coherency state is shared. The interface circuit is configured, during a response phase of the read exclusive transaction, to provide a first response indicating that the agent will provide data for the read exclusive transaction.
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SiByte, “Target Applications,” http://sibyte.com/mercurian/applications.htm, Jan. 15, 2001, 2 pages.
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Carlson Michael D.
Rowlands Joseph B.
Broadcom Corporation
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Verbrugge Kevin
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