Static information storage and retrieval – Read/write circuit – Including signal comparison
Reexamination Certificate
2000-12-26
2002-08-06
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including signal comparison
C365S210130, C365S189090, C365S189011, C365S233500
Reexamination Certificate
active
06430090
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a read device and a read method for a semiconductor memory, particularly to a read device for a semiconductor memory which reads out stored data by boosting an internal power supply voltage.
2. Description of the Related Art
Conventionally, there have been semiconductor memories in which data stored in a memory cell is read out by comparing the output voltage of the memory cell storing the data with the output voltage of a reference cell. Such semiconductor memories include non-volatile semiconductor memories in which data is stored by utilizing the difference in threshold voltage between the memory cell and the reference cell.
For example, in a stacked-gate type non-volatile semiconductor memory such as a flash memory, data is stored in a memory cell by utilizing the phenomenon that the threshold voltage varies in accordance with the number of electrons existing in the floating gate of the transistor making up the memory cell. In case of a memory cell that stores binary data, the threshold voltage of the memory cell is set to fall within one of two threshold voltage ranges.
When reading out data stored in a memory cell as described above, first, the cell current of the memory cell and that of a reference cell, which can be obtained by a read operation, are converted to voltage level signals, respectively. By comparing the voltage level signals with each other, which have been obtained as a result of the conversion, the data stored in the memory cell is read out.
FIG. 1
is a representation for illustrating a relationship among output levels (threshold voltages) of memory cells and those of reference cells in a prior art.
FIG. 1
shows the relationship among the output levels (threshold voltages) in the memory cells storing binary data.
In
FIG. 1
, the threshold voltage (V
TH1
) of a memory cell storing data ‘1’ is set to be lower than the threshold voltage (V
THe
) of an erase verify reference cell which is a first threshold voltage. The threshold voltage (V
TH0
) of a memory cell storing data ‘0’ is set to be higher than the threshold voltage (V
THw
) of a write verify reference cell which is a second threshold voltage.
The first threshold voltage (V
THe
) is set to be lower than the second threshold voltage (V
THw
), and the threshold voltage (V
Thr
) of a read reference cell is set to be between the first threshold voltage (V
THe
) and the second threshold voltage (V
THw
) . In other words, the threshold voltages are set to satisfy the relationship of V
TH0
>V
THw
>V
THr
>V
THe
>V
TH1
.
In recent years, along with the widespread use of portable information devices, a low voltage operation has been required in a non-volatile semiconductor memory. When performing a low voltage operation in a non-volatile semiconductor memory, the voltage of a word line was generally boosted so as to increase the difference between the cell current of a memory cell and that of a reference cell in the read operation, thereby reading out data stored in the memory cell. Moreover, in a non-volatile semiconductor memory, a series of read operations, including the timing to boost the voltage of the word line, etc., were controlled by a timing circuit provided in a non-volatile semiconductor memory in order to reduce the stand-by current.
FIG. 2
is a diagram illustrating an exemplary configuration of a conventional read device for a flash memory using a timing circuit.
In
FIG. 2
, reference numeral
601
denotes an address buffer. The address buffer
601
converts an externally input address to an internal address to be used in the flash memory and outputs the internal address. Reference numeral
602
denotes an address transition detection circuit. The address transition detection circuit
602
detects a change in the internal address supplied from the address buffer
601
.
If a change in the internal address is detected, the address transition detection circuit
602
outputs an address transition signal ATD, and notifies the change in the internal address to a timing circuit
612
and a word line boost circuit
603
.
The word line boost circuit
603
generates a voltage VWL for boosting one of word lines WL
0
, WL
1
, . . . , WLn which is selected by a row decoder
604
on the basis of the address transition signal ATD supplied from the address transition detection circuit
602
. The row decoder
604
selects and activates one of the word lines WL
0
, WL
1
, . . . , WLn of a memory cell array
606
according to the internal address supplied from the address buffer
601
.
Reference numeral
605
denotes a column decoder. The column decoder
605
selects and activates one of bit lines BL
0
, BL
1
, . . . , BLn of the memory cell array
606
according to the internal address supplied from the address buffer
601
. Consequently, the desired memory cell in the memory cell array
606
is selected, and the cell current indicating the stored data is supplied to a first cascade type sense circuit
607
. The first cascade type sense circuit
607
converts the cell current of the memory cell supplied from the column decoder
605
to a voltage level signal SAI, and outputs the signal to a sense amplifier
608
.
Reference numeral
609
denotes a reference word line driver. The reference word line driver
609
activates a word line for reading a reference cell
610
, based on which it is determined whether the data stored in the memory cell is ‘0’ or ‘1’. Consequently, the cell current of the reference cell
610
is supplied to a second cascade type sense circuit
611
. In order to read the reference cell
610
under the same conditions as those with the memory cell, a voltage VWL for boosting the voltage of a word line is supplied to the reference word line driver
609
from the word line boost circuit
603
. The second cascade type sense circuit
611
converts the cell current of the reference cell supplied from the reference cell
610
to a voltage level signal SAREF, and outputs the signal to the sense amplifier
608
.
The sense amplifier
608
compares the voltage value of the signal SAI supplied from the first cascade type sense circuit
607
with that of the signal SAREF supplied from the second cascade type sense circuit
611
. In accordance with the comparison result, the sense amplifier
608
determines whether the data stored in the memory cell is ‘0’ or ‘1’.
More specifically, if the voltage value of the signal SAI supplied from the first cascade type sense circuit
607
is higher than that of the signal SAREF supplied from the second cascade type sense circuit
611
by a predetermined voltage or more, the data stored in the memory cell is determined to be ‘0’. On the other hand, if the voltage value of the signal SAI supplied from the first cascade type sense circuit
607
is lower than that of the signal SAREF supplied from the second cascade type sense circuit
611
by an a predetermined voltage or more, the data stored in the memory cell is determined to be ‘1’.
A timing circuit
612
controls respective operation timings of the circuits in the read operation, e.g., the timing at which the voltage of a word line is boosted, the timing at which data is latched, etc., based on the address transition signal ATD supplied from the address transition detection circuit
602
.
Reference numeral
613
denotes a latch circuit.
The latch circuit
613
receives the data stored in the memory cell, which has been determined by the sense amplifier
608
, in response to a latch signal LT supplied from the timing circuit
612
, and temporarily stores the data. The latch circuit
613
supplies the received data to an output buffer
614
. The output buffer
614
is a transistor buffer having a high output ability, and outputs the data stored in the memory cell, which has been supplied from the latch circuit
613
, to the outside.
FIG. 3
is a diagram illustrating a circuit configuration of the first cascade type sense circuit
607
illustrated in FIG.
2
. The first cascade type sense circuit
607
comprises a l
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Nguyen Viet Q.
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