Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-07-12
2004-01-27
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C711S104000, C711S154000
Reexamination Certificate
active
06684352
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to performing read operations in static random access memory (SRAM). More particularly, the present invention relates to performing read operations within an SRAM having a way select control macro and a word select control macro.
2. The Background Art
The 6N march test algorithm is used to test internal RAM data integrity at the CPU manufacturing and debug stage and for field testing and diagnostic testing. The 6N march test consists of six(6) read/write cycles which are conducted by three march elements. Those with ordinary skill in the art shall appreciate that the six read/write operations are identified as:
↑W
o
, ↑(R
o
W
1
), ↓(R
1
W
o
R
o
)
The first march element (↑W
o
) writes a particular data background of ones and zeros into the SRAM. The first march element writes addresses from lower to higher memory addresses. The write operation of the first march element is identified as W
o
. The upward arrow, ↑, is used to designate performing either read or write operations from lower to higher memory addresses.
The second march element, ↑(R
o
W
1
), performs its read and write operations by reading and writing from the lower memory addresses to the higher memory addresses. During the first operation of the second march element, the data background from the first march test is read. This first operation of the second march element is identified as R
o
. During the second operation of the second march element, the complement of the data background is written to the SRAM addresses. The second operation of the second march element is identified as W
1
. The complement of the data background is tested to verify that the SRAM cells containing a one can store a zero and vice versa.
The third march element, ↓(R
1
W
o
R
o
), performs its read and write operation by reading and writing from the higher memory addresses to the lower memory addresses. The downward arrow, ↓, is used to represent performing read and write operations from higher to lower memory addresses. During the first operation of the third march element, the data background from the write complement, W
1
, completed in the previous march element is conducted. This first operation of the third march element is identified as R
1
. During the second operation of the third march element, the original data background is written back to the same memory locations. This second operation of the third march element is identified as W
0
. During the third operation of the third march element, the original data background is read from the same memory locations to verify the contents of each location. This third operation is identified as R
0
.
The 6N test algorithm provides a diagnostic tool for determining memory failure. When performing the 6N test algorithm, the timing for writing the test data background is determined by a scan clock signal which does not operate at the CPU operating speed. By way of example, for a 400 MHz processor, the scan clock generally operates at 50 MHz. The slower scan clock cycle presents a substantial limitation because speed related faults in the SRAM are not tested at its operating speed. Therefore, it would be beneficial to provide a memory test algorithm which can operate at the same clock cycle as the CPU.
Referring to
FIG. 1
, there is shown an illustrative SRAM unit
10
having a first memory bank or way
12
, identified as SRAM Way
0
and a second memory bank or way
14
, identified as a SRAM Way
1
. The address decoder
16
is coupled to the SRAM Way
0
,
12
, and SRAM Way
1
,
14
. The address decoder
16
receives read address signals and write address signals for both ways. Each way or bank has an associated read control module and write control module. More particularly, a read control module
18
and a write control module
20
is coupled to the SRAM Way
0
,
12
. Additionally, read control module
22
and write control module
24
is coupled to SRAM Way
1
,
14
.
Each write control module
20
and
24
includes a write enable control function and a plurality of write data ports. The write data ports write data to the cells or addresses into the SRAM unit
10
. The read control module
18
and
22
includes a plurality of read data ports which read the cells or addresses in each way.
It shall be appreciated by those of ordinary skill in the art that the illustrative SRAM unit
10
includes a row of storage cells, in which each row has one or more words. Each word is comprised of a plurality of bits. The SRAM unit stores binary information in these groups of bits which make up each word. The word is a group of bits that move in and out of storage as a unit.
During write operations of each SRAM way, a write operation is completed by writing ‘n’ bits to each address for each SRAM way. Each address is identified by the row of bits within each SRAM way. Read operations are performed differently from write operations. During read operations, the read operation is performed sequentially for each word within the row. Therefore, by way of example and not of limitation, data is read in sets of ‘n/4’, i.e. n bits divided by 4 words. To further illustrate the differences between write and read operations, it shall be appreciated by those skilled in the art that for a 256 bit write operation, a read operation would be performed with four (4) 64 bit write operations.
The different method for performing read operations and write operations creates problems when performing memory test algorithm. Memory test algorithms are used to provide high perfomance test algorithms for static random access memory (SRAM) components. An illustrative example of a variety of memory test algorithms include the 2N, 6N or 12N march test algorithms are used to test SRAM components. By way of example and not of limitation, the 6N march test algorithm uses a specific data background and the complement of the specific data background in a read/write manner which is described in further detail below.
Referring to
FIG. 2
there is shown an illustrative “macro”
50
having four embedded flip-flops
52
,
54
,
56
and
58
. The macro has a scan-in port and scan-out port accessible to the CPU only at the macro boundary flip-flops
52
and
58
. More particularly, the macro
50
consists of four embedded flip-flops
52
,
54
,
56
and
58
which are serially coupled. The first flip-flop
52
has a scan-in port that is accessible by other components and the fourth flip-flop
58
has a scan-out port that is accessible by other components. The internal coupling of the second flop
54
and the third flop
56
are not accessible. The internal coupling for the four flop macro is accomplished by coupling the first flip-flop
52
scan-out port to a scan-in port of a second flip-flop
54
, coupling the second flip-flop
54
scan-out port to the scan-in port of a third flip-flop
56
, coupling the third flip-flop
56
scan-out port to the scan-in port of the fourth flip flop
58
.
It shall be appreciated by those skilled in the art, that each flip-flop within the macro has receives an associated clocking signal from a shift clock
60
. The clocking signal “shifts” the binary data stored in each flop to the right or to the left. The clocking signal for each flip flop is determined by a shift clock
60
. The ability to control the clocking signal within each flip-flop with a shift clock is well known in the art, and is generally referred to as a shift clock.
Macros are predesigned and optimized to improve timing in the CPU. By way of example and not of limitation, a macro may include 4 to 16 flip-flops. If an input data register consists of macros instead of individual flops, the recreation of a data background by feeding the same state back into the individual flip flop is not possible. The inability to feed the same state back to the individual flops in the macro is because there are no scan-in or scan-out ports for flip flops embedded inside the macro.
Referring back to
FIG. 1
, the SRAM unit
10
may be co
Martine & Penilla LLP
Sun Microsystems Inc.
Tu Christine T.
LandOfFree
Read control system and method for testing word oriented... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Read control system and method for testing word oriented..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Read control system and method for testing word oriented... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3194643