Read circuit for accessing dynamic random access memories (DRAMS

Details Read circuit for accessing dynamic random access memories (DRAMS Read circuit for accessing dynamic random access memories (DRAMS

1993-03-03

1994-07-19

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

36518905, H03K 1708

Patent

active

053315936

ABSTRACT:
DRAM read accessing circuitry having two parallel connected control lines, one of which includes a level translator stage and the other of which includes an enable gate. Both the level translator stage and the enable gate are connected to receive 0.0 to 3 volt small logic swings from output buffer logic utilized in reading data out of the DRAM. Output signals from the level translator stage are applied to a pull up output transistor in an output driver stage, and output signals from the enable gate are connected to a pull down output transistor in the output driver stage. A feedback connection is provided between the output of the level translator stage and one input to the enable gate to ensure that the enable gate does not generate an enabling output signal for turning on the pull down output transistor until the pull up output transistor is completely turned off. Not only does this novel operation completely eliminate crossing or crossover currents in the output driver stage, but it also introduces minimum time delays in logic swings at the output node of the output driver stage.

REFERENCES:
patent: 4769561 (1988-09-01), Iwamura et al.
patent: 4779014 (1988-10-01), Masuoka et al.
patent: 4825102 (1989-04-01), Iwasawa et al.
patent: 5099138 (1992-03-01), Fukunaga
patent: 5159214 (1992-10-01), Okumura

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