Read channel circuit for optical disk reproducing apparatus

Details Read channel circuit for optical disk reproducing apparatus Read channel circuit for optical disk reproducing apparatus

1999-04-13

2001-05-22

Hindi, Nabil (Department: 2753)

Dynamic information storage or retrieval

With servo positioning of transducer assembly over track...

Optical servo system

C369S044340

Reexamination Certificate

active

06236628

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a read channel circuit of an optical disk reproducing apparatus. More particularly, the present invention relates to a read channel circuit of an optical disk reproducing apparatus which is adapted to provide stability in reproducing recorded data and performing servo control.
2. Description of the Related Art
In recent years, the development of new optical recording media and data compression techniques has made it possible to achieve enormous data storage capacity using an optical disk reproducing apparatus. The optical disk reproducing apparatus may be divided into mechanical and circuit components. Examples of the mechanical components include an optical disk, a spindle motor for rotating the optical disk, a pickup for recorded data, and driver motors for driving the pickup. Examples of the circuit components include a read channel circuit that converts signals read through the pickup to a digital data via amplifying and waveform-equalizing means before they are EFM demodulated and generates servo error signals from the read signals; a digital signal processor circuit for processing the digitalized data and restoring it to the original data as they were before modulation; an interface circuit for interfacing a data between a host computer and the optical disk reproducing apparatus; a servo processor for revising the servo error signals to control servo of the mechanical components; and a main processor or microcomputer for entirely controlling the optical disk reproducing apparatus. However, the optical disk reproducing apparatus requires revision of the offset components of mechanical and circuit components in order to secure stability of signal reproduction and servo control. In the following description, the offset resulting from the mechanical components (e.g., offset of pickup, pit depth difference) is referred to as “pit depth offset” and the revision of this offset is referred to as “offset revision”. On the other hand, the offset caused by the circuit components is simply called “offset”, with its revision being “offset revision”.
Next, the construction and operation of a read channel circuit employed in a general optical disk reproducing apparatus to revise the prescribed pit depth and offset are explained in detail with reference to
FIGS. 1 and 2
.
FIG. 1
is an exemplary diagram of a read channel circuit, in which the signals read out through the pickup of an optical disk reproducing apparatus pass through the read channel circuit before they are EFM demodulated.
FIG. 2
is an exemplary diagram illustrating another type of such a read channel circuit. Referring to
FIG. 1
, the signals read by four-division photodiodes (hereafter, referred to as “PDs ”) A to D are amplified as voltages at I/V amplifiers
102
,
104
,
106
and
108
and sent to a data reproducing section
200
, a tracking error signal detecting section
300
and a focusing error signal detecting section
400
.
The read signals A to D applied to the data reproducing section
200
are gain-controlled and summed by an AGC (Automatic Gain Control) & sum circuit
202
, and output as an RF signal A+B+C+D. This RF signal is equalized by a waveform equalizer circuit
204
and shaped as a rectangular wave pulse via a data slice circuit
206
. The EFM signal digitalized by the data slice circuit
206
is demodulated into the data as they were before EFM modulation at a DSP (Digital Signal Processor)
208
, and output to a host computer via an interface (not shown).
On the other hand, the read signals A to D applied to the tracking error signal detecting section
300
is delay-adjusted by delay circuits
310
,
312
,
314
and
316
, which are connected to the outputs of buffers
302
,
304
,
306
and
308
, respectively, and input to adders
318
and
320
. Delay control signals DCS(1) and DCS(2) are input to the delay circuits
310
,
312
,
314
and
316
to be used for pit depth revision. Under these signals, the read signals A to D are tuned and output. DCS(1) and DCS(2), although not shown, can be output either from the servo processor or from the main processor.
The read signals A and C output from the delay circuits
310
and
314
are summed and amplified at an AGC & sum circuit
318
and compared with a reference voltage level V
ref
at a level comparator
322
, which outputs the comparison result as a digital data. Level comparator
324
also compares the sum B+D of read signals B and D with the reference voltage level V
ref
, outputting the result as digital data. These digital data output from the two level comparators
322
and
324
are delay-controlled under DCS(3) and DCS(4) at first and second delay circuits
326
and
328
, respectively, and supplied to a phase detector
330
. DCS(3) and DCS(4) denote delay control signals used to revise the offset component of the circuit components. The delay control signals can also be output either from the servo processor or from the main processor. The phase detector
330
outputs a voltage signal based on the phase difference between signals A+C and B+D. The output voltage signal is filtered at an LPF (Low Pass Filter)
332
and output as a tracking error signal (hereinafter, referred to as “TES”). As well as a focusing error signal (hereinafter, referred to as “FES”) that will be described later, TES is input to the servo processor (not shown) and used to perform a servo control.
Each of the read signals A to D applied to the focusing error signal detector
400
is amplified and summed at sum & amplifiers
402
and
404
, and output as signals A+C and B+D, which signals are compared by a level comparator
406
. The data according to the comparison result is filtered at LPF
408
and output as a focusing error signal.
In an optical disk reproducing apparatus employing the above-described read channel circuit, distortion of signals due to analog signal processing increases with higher processing rate. Especially, the waveform equalizer circuit
204
that processes analog signals is more variable in characteristic as the processing rate becomes higher, so that stability of the output signal is hard to secure, with a consequence of difficulty in an aspect of design. Higher processing rate also gives a rise to an increase in the power consumption of analog signal processing devices. Another problem with such an optical disk reproducing apparatus is that there is much difficulty in controlling delay characteristic for revising pit depth and the offset component of the circuit components, as a result of which precise servo control is impossible to achieve.
Next, the construction and operation of another read channel circuit are explained in detail with reference to FIG.
2
. The tracking error signal detecting section
300
and the focusing error signal detecting section
400
of the lead channel circuit shown in
FIG. 2
are same in construction as shown in
FIG. 1
, and their constructions and functions will be omitted in the following description.
In the construction and operation of data reproducing section
200
, the read signals picked-up by four-division PDs A to D are amplified as voltages at I/V amplifiers
102
,
104
,
106
and
108
and sent to the AGC & sum circuit
202
of the data reproducing section
200
. Those read signals are gain-controlled and summed at the AGC & sum circuit
202
and removed of noises at an anti-aliasing filter
210
. The read signals are sampled by a sampling clock SCLK and output as a digital data, which undergoes waveform equalization and low pass filtration at a digital waveform equalizer circuit/LPF
214
and is supplied to a timing recovery circuit
218
and a DSP
216
. The timing recovery circuit
218
generates a control voltage (as a digital data in case of digital phase-locked loop) based on the difference between the read signal output from the waveform equalizer circuit/LPF
214
and a reference sampling point. A voltage-controlled oscillator (VCO)
220
generates a samplin

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