Read channel circuit and method for decoding using...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S746000

Reexamination Certificate

active

06757863

ABSTRACT:

CROSS-REFERENDE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No.2000-283850, filed on Sep. 19, 2000; the entire contents of which are incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a read channel circuit and method for decoding using reduced-complexity error correction. More particularly, the present invention relates to a technology for providing a read channel circuit which has a decoding function applicable to high channel frequencies for decoding a modulated reception signal and is favorably applicable to an optical disk playback equipment such as a DVD, a CD-ROM, or a MD player.
2. Description of the Related Art
FIG. 1
illustrates a conventional read channel circuit applicable to a playback equipments such as a DVD player.
Such a conventional read channel circuit comprises, as shown in
FIG. 1
, a comparator
70
, a slice level generator
71
, a channel clock generator
72
, and a flip-flop
73
.
The comparator
70
is fed at the positive electrode (+) terminal and the negative electrode (−) terminal with a reception signal (a playback signal) received at the read channel and a slice level signal generated by the slice level generator
71
, respectively. The output of the comparator
70
is a low (L) level signal when the input voltage level of the negative electrode is greater than that of the positive electrode, and is a high (H) level signal when the input voltage level of the negative electrode is lower than that of the positive electrode. Therefore, the output of the comparator
70
is a binary signal. The binary signal output of the comparator
70
is then transferred to the slice level generator
71
, the channel clock generator
72
, and the flip-flop
73
.
The slice level generator
71
is responsive to the output signal from the comparator
70
for controlling the voltage of the slice level signal so as to have an average duty ratio of 50%.
The channel clock generator
72
generates a channel clock synchronized in phase with the binary signal from the comparator
70
and transfers the binary signal to a clock terminal of the flip-flop
73
. The operation of the channel clock generator
72
shown in
FIG. 1
synchronizes the polarity inverted phase of the binary signal with the falling edge phase of the channel clock and sets the duty ratio of the channel clock to 50%. The channel clock generator
72
may be implemented by a PLL (phase locked loop) circuit.
The flip-flop
73
samples the binary signal received at its data input terminal from the comparator
70
at the timing of each rising edge of the channel clock. A sampled signal output from the flip-flop
73
is then transferred as a channel stream signal to a given processor circuit provided at the succeeding stage of the flip-flop
73
.
The conventional read channel circuit described above however has the following technical problems.
The technical problems in the conventional read channel circuit will now be described referring to FIG.
2
. As shown in
FIG. 2
, denoted by (
1
) is a received signal which may represent a pattern of pits provided on a DVD disk. It is also assumed that the signal (
1
) is encoded by RLL (run-length limited coding) (
2
,
10
). In the RLL (
2
,
10
), the minimum code inverted length is 3T and the maximum code inverted length is 11T (T represents one channel cycle).
Also, a signal (
2
) is an ideal received signal from an optical playback path of DVD system as the transmission path. A signal (
3
) is a slice level signal. A signal (
4
) is a noise signal superimposed on the transmission path. A signal (
5
) is a received signal superimposed with the noise signal (
4
). A signal (
6
) is an ideal slice level signal. Note that the signal (
5
) is equivalent to a sum of the two signals (
2
) and (
4
).
A signal (
7
) is a binary signal outputted from the comparator
70
in response to the input of the signal (
2
). A signal (
8
) is another binary signal outputted from the comparator
70
in response to the input of the signal (
5
). A signal (
9
) is a channel clock synchronized with the signal (
7
) or (
8
). A signal (
10
) is a channel stream signal generated by decoding the signal (
2
). A signal (
11
) is another channel stream signal generated by decoding the signal (
5
).
As apparent from
FIG. 2
, the channel stream signal (
10
) from the decoding of the signal (
2
) is equal in the encoded form to the transmission signal (
1
) and can thus be decoded without any error. On the other hand, the channel stream signal (
11
) from the decoding of the signal (
5
) having noise components added is not equal in the encoded form to the transmission signal (
1
) as containing errors in the proximity of moments t
2
, t
5
, t
7
and t
8
.
In other words, in the conventional read channel circuit, as the noises are superimposed at given levels and given moments on the transmission path, they may result in errors on the channel stream signal. The noises on the transmission path in a DVD player may derive from fault formation of pits, tilting of the optical axis of an optical pickup from the vertical to a disk surface, tracking error, or leak signals of any adjacent track in accordance with deviance in tracking control.
There is commonly proposed a scheme for adding an error correction code to a digital code signal which is carried along the transmission path failing to inhibit the introduction of noises.
Such a scheme may be favored when the number of errors developed on the channel stream signal stays within a range of the capability of error correction of the error correction code. However, if errors exceed the range, they will hardly be eliminated hence making the receive signal incorrect. Alternative technologies are thus desired for minimizing the development of errors on the channel stream prior to the step of error correction with the error correction code.
One of them is disclosed in Japanese Patent Laid-open Application No. PH9-8674 where the development of errors on the channel stream prior to the step of error correction is minimized by means of a maximum likelihood decoder using Viterbi algorithms.
FIG. 3
illustrates a read channel circuit equipped with the maximum likelihood decoder.
The read channel circuit with the maximum likelihood decoder shown in
FIG. 3
comprises an analog/digital converter (ADC)
75
, an adder
76
, a slice level generator
77
, a channel clock generator
78
, and the maximum likelihood decoder
79
.
The ADC
75
samples the received signal at the timing of the channel clock generated by the channel clock generator
78
and quantizes a sampled signal to data of a specific number of bits (for example, 8 bits) which is then transferred as a multi-level signal to the adder
76
.
The adder
76
adds the multi-level signal from the ADC
75
with a slice level signal from the slice level generator
77
to have an offset multi-level signal which is transferred to the maximum likelihood decoder
79
. Also, sign bit of the offset multi-level signal output of the adder
76
is transmitted to the slice level generator
77
and the channel clock generator
78
.
The slice level generator
77
upon receiving the signal output from the adder
76
generates a slice level to have an average duty ratio of 50%. The slice level generator
77
and the adder
76
generates in a combination an auto slice signal which is received by both the channel clock generator
72
and the maximum likelihood decoder
79
.
The channel clock generator
78
generates a channel clock synchronized in phase with the sign bit of the offset multi-level signal from the adder
76
. The generated channel clock is transferred as a sampling clock signal to the ADC
75
and as an operating clock signal to the slice level generator
77
and the maximum likelihood decoder
79
. The channel clock generator
78
may be implemented by a PLL circuit, for example.
The maximum likelihood decoder
79
decodes the rece

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