Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2000-02-29
2003-05-20
Nguyen, T. V. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S154000, C711S155000, C711S156000, C711S157000, C711S167000, C711S168000, C711S169000, C712S207000, C712S237000
Reexamination Certificate
active
06567901
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method of handling memory reads in a computer system and, more particularly, to a method that indicates to a computer's memory subsystem that a current read request is speculative so that the subsystem can service non-speculative read requests first.
2. Description of the Related Art
With the ever-increasing amount of data being processed by today's computer systems, the efficient use of computer resources is very important. The processing power of computer systems is often increased by adding processors. In today's multi-processor computer systems, memory read requests are typically serviced on a first-come-first-served basis, and a processor that has issued a memory request might be paused by other requests that are ahead of it in the memory subsystem. The memory subsystem can be a bottleneck in processing speed because the memory subsystem's physical devices typically operate more slowly than a computer's processor or because multiple processors are using the same memory subsystem. To address this concern many processors issue read requests before data is actually needed and often even before it is known whether the data will ever be needed. An example of this occurs when a processor approaches a branch. Not knowing which path of a program will be executed, a processor may request the data necessary for both paths so that the program, when it reaches the branch, can continue regardless of the path chosen. This typically helps the performance of a processor in a single processor system, but in a multiple processor system memory bandwidth is limited and these extra requests can hurt the performance of other processors in the system. Being able to cancel unneeded memory cycles in that case would be particularly beneficial.
Another example of a processor performing operations that are speculative is when a processor, such as the PENTIUM® Pro manufactured by the Intel Corporation of Santa Clara, Calif. utilizes “speculative execution.” Speculative execution is a mechanism in which the processor maintains an “instruction queue,” looks ahead in the instruction queue and performs instructions out of order rather than waiting for unread operands. The results of the out-of-order instructions are stored in an “instruction pool.” Once it is apparent that an instruction is necessary and all previous instructions in the queue have been completed, the results stored in the instruction pool are committed to memory, either registers, RAM, or disk. When an instruction is a branch, the processor typically makes a guess as to the most likely path. If the guess is ultimately wrong, the processor clears the unneeded instructions and results from the instruction pool.
In the speculative execution environment, a read request may also be marked speculative if it is uncertain whether the value of an operand might change after the instruction is executed but before the result is committed. In that case, the instruction needs to be re-executed with correct data before the result is committed.
Although current processors typically speculate concerning instructions and data that might be needed, current memory subsystems are designed to service memory requests in a first-come-first-served order.
SUMMARY OF THE INVENTION
In a system implemented according to the invention, a processor initiates memory read transactions on a bus, and when the read is a speculative load, the processor provides information regarding the speculative nature of the transaction. A bus device, such as a memory controller, then receives the transaction and places the request in a queue to be serviced in an order dependent upon the relative speculative nature of the request. Transactions that are “non-speculative” are serviced before transactions that are “speculative.”
In addition, the bus device, upon receipt of an appropriate signal, cancels a speculative read that is no longer needed or upgrades the priority of a speculative read that has become non-speculative. If data required for a load is not available in a computer's random access memory (RAM) or cache memory, a page fault typically occurs, resulting in a disk read. In the case of a speculative load that is ultimately cancelled, by “putting off” the speculative load, an unnecessary page fault (and the resulting disk read) might be prevented.
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Fletcher Yoder & Van Someren
Hewlett -Packard Development Company, L.P.
Nguyen T. V.
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