Read approach for multi-level virtual ground memory

Details Read approach for multi-level virtual ground memory Read approach for multi-level virtual ground memory

2006-05-02

2006-05-02

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185240, C365S189070

Reexamination Certificate

active

07038948

ABSTRACT:
The present invention pertains to a technique for determining the level of a bit in a dual sided ONO flash memory cell where each of the bits of the dual sided ONO flash memory cell can be programmed to multiple levels. One or more aspects of the present invention take into consideration the affect that the level of charge on one bit can have on the other bit, otherwise known as complimentary bit disturb. A metric known as transconductance is utilized in making the bit level determination to provide a greater degree of resolution and accuracy. In this manner, determining the bit level in accordance with one or more aspects of the present invention mitigates false or erroneous reads.

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