Read and writable data bus particularly for programmable logic d

Details Read and writable data bus particularly for programmable logic d Read and writable data bus particularly for programmable logic d

1996-02-02

1997-06-03

Hudspeth, David R.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 41, 326 86, H03K 19177

Patent

active

056358512

ABSTRACT:
A data bus on an integrated circuit includes a series of selectors arranged in a ring, each selector having an output terminal, an enable terminal, a ring input terminal, and a data input terminal. The ring input terminal receives data from another selector in the ring. The data input terminal receives data from a data source. The output terminal supplies data to the ring input terminal of a next selector in the ring. The enable terminal receives enable signals from a data source. A selector either propagates the signal on its ring input terminal or a data signal on its data input terminal to the next selector.

REFERENCES:
patent: 5073730 (1991-12-01), Hoffman
patent: 5099148 (1992-03-01), McClure et al.
patent: 5229657 (1993-07-01), Rackley
patent: 5241221 (1993-08-01), Fletcher et al.
patent: 5483177 (1996-01-01), Van Lieverloo

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