Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2001-03-06
2002-09-17
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S189090
Reexamination Certificate
active
06452850
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a sense amplifier and to a DRAM memory that includes the sense amplifier.
DRAM memories (Dynamic Random Access Memories) constitute an important type of memory for storing digital information. They are memories in which, after the specification of an address, data can be stored and read out again under this address. In this case, the information is stored as a quantity of charge on a capacitance. Therefore, a DRAM memory cell is constructed very simply since it can comprise merely a capacitance and a selection transistor.
DRAM memories usually have a number of DRAM memory cells which are each combined to form one or more memory cell arrays. The individual memory cells are wired to the periphery by word lines and bit lines. The bit line wiring in this case defines a grid into which read/write amplifiers are also inserted. The read/write amplifiers have the task of amplifying voltage values read from the bit lines to correspondingly predetermined levels, so that these voltage values can be evaluated and processed further in a suitable manner.
In order to read a DRAM memory cell, the latter is firstly activated via a word line. Afterwards, the memory cell can be read by the information stored in it being fed as a voltage signal via the bit line to the read/write amplifier. In order to be able to correctly evaluate the information content of the memory cell, it is furthermore necessary to compare the information read out via the bit line of the memory cell to be read, or the corresponding voltage signal, with a reference voltage signal. To that end, the read/write amplifier is furthermore connected to at least one reference bit line, which is in turn connected to a memory cell which is currently not being evaluated.
In order to be able to evaluate the voltage signals read from the memory cell to be evaluated, they must be correspondingly amplified. To that end, the read/write amplifier generally has one or more sense amplifier subcircuits. The sense amplifier subcircuit of a DRAM memory has the task of amplifying a small voltage signal, which results from the voltage level stored in the memory cell, reliably and quickly to full levels.
Depending on the information content of the memory cell to be read, the voltage level has to be amplified to a low or high level. A low level is produced by means of a sense amplifier subcircuit referred to as an N latch. A high level is produced by means of a sense amplifier subcircuit referred to as a P latch.
In the case of the “mid-level” evaluation scheme which is customary nowadays, the bit line level at the beginning of the evaluation is at half the array voltage. In this case, the array voltage corresponds to the high level. Using an example, if the low level has a value of 0 volts, for example, and the high level has a value of 2 volts, for example, this means that the bit line level at the beginning of the evaluation is at 1 volt.
The sense amplifier subcircuits usually have at least two evaluation transistors which may be designed for example, but not exclusively, as “field-effect transistors”. The field-effect transistor (FET) is a semiconductor device having three terminals, which are designated by gate (G), source (S) and drain (D).
An important parameter in field-effect transistors is the “threshold voltage”. This is that voltage starting from which a drain current flows in the transistor. That is to say the transistor opens. This means that, starting from the threshold voltage, the potential barrier in the transistor is reduced to such an extent that a current can flow. If a reverse voltage is applied between source and bulk, the value of the threshold voltage increases since the potential barrier increases. The bulk of the transistor is a fourth terminal, which results from the common carrier, usually a semiconductor carrier, and is also designated by substrate.
Sense amplifier subcircuits for a DRAM memory for amplifying voltage signals read from a bit line generally have at least two such evaluation transistors, the gate of one transistor being connected or connectable to at least one bit line and the gate of another evaluation transistor being connected or connectable to at least one reference bit line. Furthermore, the drains of the evaluation transistors are connected or connectable to bit lines and the sources of the evaluation transistors are connected or connectable to a lead. The lead, which is also designated as “NCS” in N latch sections or, respectively, is also designated as “PCS” in P latch sections, is a line via which the sense amplifier circuit is activated.
If, in the “mid-level” evaluation scheme, the bit line level at the beginning of the evaluation is at approximately half the array voltage, this voltage level also corresponds to the gate-source voltage across the evaluation transistors. In order to achieve the evaluation with the necessary speed, the gate-source voltage must lie above the threshold voltage of the evaluation transistors by a sufficiently high magnitude. For reasons of line density and reliability, the array voltage is scaled downward with diminishing feature sizes, that is to say with advancing DRAM generations. Since the threshold voltage of the evaluation transistors cannot be reduced to the same extent as the array voltages, the distance between the initial bit line level—for example half the array voltage, which corresponds to half the supply voltage—and the threshold voltage of the evaluation transistors becomes smaller and smaller. The evaluation transistors “open” less and less and the evaluation thus requires more and more time. It is very disadvantageous, however.
When “SOI transistors” are used, it is possible to control the substrate potential of a transistor with a low power consumption. The designation “SOI” denotes “silicon on insulator”. Transistors of this type have recently acquired more and more importance. SOI transistors are already known per se from the prior art.
SOI transistors open up the possibility of using a substrate control effect to influence the threshold voltage of the evaluation transistors in a positive way for the evaluation speed. The substrate, or the bulk of the transistor, is also referred to as the body in SOI transistors.
The prior art has already disclosed a number of possible solutions to enable the threshold voltage of evaluation transistors designed as SOI transistors to be influenced by means of the substrate control effect. These solutions are illustrated in
FIGS. 1
to
3
and are explained in more detail in the context of the description of the figures.
In the embodiment illustrated in
FIG. 1
, the voltages across the sense amplifier subcircuit of a conventional sense amplifier, said subcircuit being designed as an N latch, are shown at the beginning of the evaluation operation. There is a negative voltage between source and body, said voltage increasing the threshold voltage of the transistors on account of the substrate control influence. This is disadvantageous, however, for the reasons mentioned above.
FIG. 2
illustrates the principle of “body synchronous sensing”, in which the undesirable threshold voltage increase is avoided by source and body being kept at the same potential.
FIG. 3
illustrates the circuitry of the N latch section of a sense amplifier in the case of “super body synchronous sensing”. The body voltage can be set via a separate line. At the beginning of the evaluation, the body voltage is set such that the source-body voltage becomes positive and the threshold voltage of the evaluation transistors is thus reduced by means of the substrate control influence. However, a positive source-body voltage means that the source-bulk diodes are forward-biased. Therefore, the sensing scheme can only be used for voltage levels at which the resulting forward current is small enough that it does not have a disadvantageous effect. The last-mentioned solution is described for example in the paper “SOI-DRAM Circuit Technologies for Low Power High Speed Multi
Frey Alexander
Weber Werner
Greenberg Laurence A.
Infineon - Technologies AG
Le Thong
Locher Ralph E.
Nelms David
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