Read amplifier for semiconductor memory cells with means to comp

Details Read amplifier for semiconductor memory cells with means to comp Read amplifier for semiconductor memory cells with means to comp

1998-11-12

2000-02-22

Nelms, David

Static information storage and retrieval

Read/write circuit

Differential sensing

365207, 365205, G11C 702

Patent

active

060288035

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

European reference 0 549 623 B1, or respectively, from the corresponding U.S. Pat. No. 5,333,121, a read amplifier according to the preamble of patent claim 1 is known.
In future DRAM memory generations with a memory capacity of 1 Gbit and more, problems with the mismatch of transistors will increase considerably. In principle, variations in the inception voltage and in the drain current are thereby involved, whereby the first make up approx. 65 to 100 percent of the overall effect. The variations in the inception voltage are proportional to 1/.sqroot.gate surface, and consequently increase as the transistor surfaces decrease. The degree of agreement of two transistors required in read amplifiers thus necessarily becomes increasingly worse as progress is made in miniaturization. Previously, the problem was solved above all by increasing the surface of the cross-coupled transistors present in the read amplifier. This procedure will presumably come to an end with 4 GBit memories at the latest, because there the surface required for the cross-coupled transistor pair of the read amplifier exceeds 25 percent of the overall chip surface due to the mismatch problem alone.
From the IEEE Journal of Solid-State Circuits, vol. SC-14, no. 6, December 1979, pages 1066 to 1070, a read amplifier is known that comprises a means for compensation of threshold voltage differences with four MOS transistors. However, this circuit has for example the disadvantage that its compensation effect depends on a relation of circuit-internal capacitors, and remains incomplete.
From the IEEE publication IEDM 1981, pp. 44-47, a read amplifier is known that requires an additional transistor for equalizing the bitlines, and requires an additional connection line for the supply voltage.


SUMMARY OF THE INVENTION

The underlying object of the invention is to indicate a semiconductor memory with a read amplifier in which the above named disadvantages are avoided.
In general terms the present invention is a semiconductor memory with a read amplifier. The read amplifier is connected with a bitline pair, whereby a first bitline of the bitline pair is connected with a memory cell and a second bitline represents a comparison line. Two cross-coupled MOS transistors form a holding element. These MOS transistors respectively form a first terminal that is connected with an activation input of the read amplifier. A second terminal of a first of these two MOS transistors is connected with the first bitline and a second terminal of a second of these two MOS transistors is connected with the second bitline. Two additional MOS transistors have gates connected with a first control line. A respective first terminal of these two additional MOS transistors is respectively connected with one of the gates of the cross-coupled MOS transistors. The gate of the first of the cross-coupled MOS transistors can be connected with the second bitline via a first further MOS transistor. The gate of the second cross-coupled MOS transistor can be connected with the first bitline via a second further MOS transistor. The gates of the two further MOS transistors are connected in common with a second control line. The additional MOS transistors has second terminals that are connected in common with the activating input of the read amplifier.
Advantageous developments of the present invention are as follows.
The two additional MOS transistors and the two further MOS transistors are all n-channel MOS transistors.
The two cross-coupled MOS transistors are n-channel MOS transistors in one embodiment, and in another embodiment the two cross-coupled MOS transistors are p-channel MOS transistors.
A particular advantage of the invention is that by means of a corresponding control unit, the four additional transistors can also be used as an equalizing means (equalize) for the two bitlines, and thus only one additional transistor is required in relation to conventional read amplifiers.


BRIEF DESCRIPTION OF THE DRAWINGS

The features of the present invention

REFERENCES:
patent: 3879621 (1975-04-01), Cavaliere et al.
patent: 4238841 (1980-12-01), Clement et al.
patent: 4858195 (1989-08-01), Soneda
patent: 4879684 (1989-11-01), Krauss et al.
patent: 5023841 (1991-06-01), Akrout et al.
patent: 5333121 (1994-07-01), Geib
patent: 5859794 (1999-01-01), Chan
IEEE Journal of Solid-State Circuits, vol. SC-14, No. 6, Dec. (1979), S. Suzuki et al, "Threshold Difference Compensated Sense Amplifier", pp. 2066-1070.
IEEE publication IEDM (1981), T. Furuyama et al, "A New Sense Amplifier Technique for VLSI Dynamic RAM's", pp. 47-44.

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