Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2006-01-19
2009-11-17
Puente, Emerson C (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S010000, C709S226000
Reexamination Certificate
active
07620841
ABSTRACT:
A method and apparatus for re-utilizing partially failed compute resources in a massively parallel super computer system. In the preferred embodiments the compute node comprises a number of clock domains that can be enabled separately. When an error in a compute node is detected, and the failure is not in network communication blocks, a clock enable circuit enables the clocks to the network communication blocks only to allow the partially failed compute node to be re-utilized as a network resource. The computer system can then continue to operate with only slightly diminished performance and thereby improve performance and perceived overall reliability.
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Chen Dong
Gara Alan
Heidelberger Philip
Liebsch Thomas Alan
Steinmacher-Burow Burkhard
International Business Machines - Corporation
Martin & Associates LLC
Mehrmanesh Elmira
Petersen Bret J.
Puente Emerson C
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