Re-programmable logic array

Details Re-programmable logic array Re-programmable logic array

2002-04-23

2004-02-17

Cho, James D. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S101000

Reexamination Certificate

active

06693453

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to circuitry, and more particularly, to programmable logic array circuitry that enables flexible programming and re-programming.
2. Description of the Related Art
In some control units, random logic combinational circuits are often required to generate control signals. To implement such functions, PLAs (programmable logic arrays) become a general solution. Traditional PLAs, such as PLA
10
of
FIG. 1
, are defined as a matrix that includes inverter (INV) arrays
12
, AND arrays
14
, OR arrays
16
, and the like. In such example, the logic gates are electrically connected to one another.
The programming rule is hard-wired by blowing (e.g., burning) fuses
18
. The concept and implementation of PLAs are therefore quite straightforward. However, once programming is executed, the PLA can no longer be modified. In other words, it lacks re-programming capability. This drawback therefore introduces a costly inconvenience to both end users as well as system designers. Designers will thus be forced to purchase new hardware to implement a new design change or accommodate some unanticipated use by a customer.
In view of the foregoing, there is a need for a logic array circuitry that can easily be re-programmed to account for changes in design or end-user implementation.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills this need by providing programmable logic array circuitry that can easily be re-programmed. The re-programmability of the logic array provides for more flexible design options and reduces the cost of hardware and re-engineering. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, a system, or a device. Several inventive embodiments of the present invention are described below.
In one embodiment, a logic array is provided. The logic array at least one input and at least one output. An input capacitive device is coupled to the at least one input. Internal gating devices are coupled to the input capacitive device, and an output capacitive device is coupled to the internal gating devices and the at least one output. Signal generating circuitry for controlling the internal gating devices is further provided. The internal gating devices are designed to be controlled to establish a connection between one of the at least one input and one of the at least one output.
In another embodiment, a re-programmable logic array (RPLA) is provided. The RPLA includes at least one input and a plurality of outputs. An input capacitive device is coupled to the at least one input. Internal gating devices are coupled to the input capacitive device. A plurality of output capacitive devices is further provided. Each output capacitive device is coupled to one of the internal gating devices and one of the plurality of outputs. Signal generating circuitry is provided for controlling the internal gating devices. The internal gating devices are controlled to establish a connection between one input and one of the plurality of outputs.
In yet another embodiment, a re-programmable logic array (RPLA) is provided. The RPLA includes an input and an output. An input capacitive device is coupled to the input. A plurality of selectable logic blocks is provided. Each selectable logic block is coupled to the input capacitive device. A plurality of internal gating devices is provided, and each of the internal gating devices is coupled to respective ones of the plurality of selectable logic blocks. Further included in the RPLA is an output capacitive device. The output capacitive device is coupled to each of the internal gating devices and the output. Signal generating circuitry for controlling the internal gating devices is provided. The internal gating devices are controlled to establish a connection between the input, one of the selectable logic blocks, and the output.
The advantages of the present invention are numerous. Most notably, however, is that the RPLA of the present invention is more flexible that prior art PLA's that require the blowing of fuses to complete programming designs. By providing the sample and hold (S/H) circuitry of the present invention, generated control signals enable fast and efficient programming of the RPLA. The S/H circuitry, as will be understood by one skilled in the art, will enable synchronization with the system clock (CK) and application to a pipeline system. Furthermore, the RPLA can be re-utilized, which makes hardware circuitry reusable and beneficially enables a reduction in system hardware cost.


REFERENCES:
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patent: 4724341 (1988-02-01), Yamada et al.
patent: 4902917 (1990-02-01), Simpson
patent: 5387827 (1995-02-01), Yokoyama et al.
patent: 6020776 (2000-02-01), Young
patent: 01109921 (1989-04-01), None
Rhyne, Fundamental of Digital Systems Design, NJ, 1973, pp. 70-71.*
Taub et al., Digital Integrated Electronics, 1977, McGraw-Hill, pp. 98-99.

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