RC netlist reduction for timing and noise analysis

Details RC netlist reduction for timing and noise analysis RC netlist reduction for timing and noise analysis

2001-12-28

2004-03-09

Whitmore, Stacy A. (Department: 2812)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06704911

ABSTRACT:

BACKGROUND OF INVENTION
The capabilities of modern integrated circuits (“ICs”) continue to increase as technology improves. In order to increase the capabilities of an IC without increasing the size of the IC, sizes of devices on the IC must often be reduced to units of microns (10
−6
). Circuit designs using devices having sizes measurable in microns are known and referred to as deep submicron (“DSM”) designs.
A typical IC having a DSM design has tens of millions of devices. With this increased number of devices, there are more devices per unit area than a non-DSM design IC. To connect the devices to the IC substrate itself and with other circuit devices and components, physical wires, known as interconnect, form a network of connections on the IC. From a technical viewpoint, interconnect does not behave as a virtual or ideal wire. Instead, the interconnect acts similarly to a network of capacitances and resistors, which can dominate circuit behavior, particularly with regard to timing.
FIG. 1
shows a section of interconnect (
10
) on a typical IC (
12
). The interconnect (
10
) have inherent resistances (not shown) and capacitances (
14
). The section of interconnect (
10
) shown in
FIG. 1
is typically part of a larger network of interconnect known and referred to as a “RC network.”
As the number of interconnect in a RC network increase with more devices per unit area on a DSM design IC, device performance, e.g., timing, signal integrity, power problems, etc., coupled with the demands for increased reliability, speed, and efficiency becomes increasingly harder to manage. In order to meet such demands, chip designers use automated tools to verify physical design and ensure circuit integrity.
One method used to facilitate the analysis and testing of an IC's interconnect is parasitic extraction. Parasitic extraction is the process of creating an electrical model representation of the physical connections present between devices in an IC. The electrical model formed as a result of parasitic extraction is typically known and referred to as a “netlist.”
Reduction entails removing unintentional circuit elements to ensure circuit integrity. One goal of typical reduction techniques is to make a netlist as compact as possible while preserving accuracy as much as possible.
FIGS. 2
a
and
2
b
respectively show an original circuit (
20
) before a typical reduction process and a reduced circuit (
30
) after the typical reduction process. As shown in
FIG. 2
b
, a topology of the reduced circuit (
30
) is different from a topology of the original circuit (
20
). Further, the reduced circuit (
30
) has resistive loops (
32
) that were not present in the original circuit (
20
). Further still, the reduced circuit (
30
) has ground resistances (
34
) that were not present in the original circuit (
20
).
In effect, the typical reduction process results in a netlist that is topologically and functionally different from an original circuit. In addition, with a typical reduction process, because modern circuits have large numbers of input/output ports, there is a tendency for the reduction process to couple input/output ports with each other; thereby actually increasing the size of the circuit. Thus, there is a need for a reduction process that maintains an original circuit's topology while maintaining functional accuracy in a netlist with respect to the function and characteristics of the original circuit.
SUMMARY OF INVENTION
According to one aspect of the present invention, a circuit reduction method comprises inputting information about an original circuit structure, using a resistive degree of at least one node in the original circuit structure to selectively sort the at least one node, determining at least one time constant of the original circuit, sorting the at least one time constant, and determining whether to remove a loop in the original circuit structure based on the sorted at least one time constant and the sorted at least one node.
According to another aspect, a computer-readable medium having recorded therein instructions executable by processing, where the instructions are for: inputting information about an original circuit structure; using a resistive degree of at least one node in the original circuit structure to selectively sort the at least one node; determining at least one time constant of the original circuit; sorting the at least one time constant; and determining whether to remove a loop in the original circuit structure based on the sorted at least one time constant and the sorted at least one node.
According to another aspect, a computer system comprises a processor, a memory, and instructions that reside in the memory and are executable by the processor, where the instructions are for: inputting information about an original circuit structure; using a resistive degree of at least one node in the original circuit structure to selectively sort the at least one node; determining at least one time constant of the original circuit; sorting the at least one time constant; and determining whether to remove a loop in the original circuit structure based on the sorted at least one time constant and the sorted at least one node.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 6014510 (2000-01-01), Burks et al.
Sheehan, Bernard, et al., “TICER: Realizable reduction of extracted RC circuits”, 1999, IEEE, pp. 1-4.*
Mentor Grpahics, Bernard, et al., “TICER: Realizable reduction of extracted RC circuits”, 1999, http://www.mentor.com.com/, pgs.*
Mauss, Jakob, et al., “Qualitative resoning about electrical circuits using series-parallel-star trees”, 1996, www9.in.turn.de/personen/mauss/publications/MaussNeumann96a.pdf, pp. 1-13.*
Ajluni, Cheryl, “Parasitic extraction tools aid DSM IC designs”, 1997, www.elecdesign.com/Globals/PlanetEE/Content/827.html, pp. 1-11.

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