Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2000-08-21
2002-06-11
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S083000, C326S112000
Reexamination Certificate
active
06404238
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a logic gate and more specifically to an FET logic gate of the so-called ratio logic family.
BACKGROUND OF THE INVENTION
There is known in the art a number of different logic families, one of which is termed ratio logic. In ratio logic a pull-up device is connected between a high supply potential and a circuit node and a number of pull-down devices are connected between the circuit node and a negative supply potential. The pull-up device is permanently enabled and thus the circuit node is at a high potential provided the pull-down device are all inoperative. When one or more pull-down devices operates then the circuit node is at a relatively low level. Typically the pull-up device is a PMOS transistor and the pull-down devices are NMOS transistors.
There is then the requirement that the PMOS transistor must be of weaker conductivity than one NMOS, otherwise the output node will not be pulled down sufficiently to indicate a change in logic state.
The requirement for a weak PMOS extends the pull-up time of the circuit node. This is because allowance must be made during design for the p transistors of a circuit to be at the strong end of their tolerance and the n transistors to be at the weak ends of their tolerance. Then, when the opposite process conditions appear, namely the p transistors being weaker than expected and the n transistors being stronger than expected the pull-up time may be excessive; it is this worst case rise time which is specified for the circuit.
It is accordingly an object of the present invention to at least partially mitigate the difficulties of the prior art.
SUMMARY OF THE INVENTION
According to the present invention there is provided a logic gate comprising a current mirror circuit having a supply node, a first node and a second node wherein application of a first current at the first node causes a second current at the second node, plural input pull-down transistors connected between a reference node and one of said first and second nodes, and an output pull-down transistor connected between the other of said first and second nodes, and the reference terminal wherein the supply node has a connection to a supply terminal, the plural input pull-down transistors have respective control terminals connected to a corresponding plurality of input terminals and the output pull-down transistor has circuitry connected to its control node for biasing it on wherein said input pull-down transistors are mutually substantially identical and wherein said output pull-down transistor is smaller than each said input pull-down transistor.
Conveniently said plural input transistors are connected to said first node.
Preferably the current mirror circuit has a pair of FETs having a common drain/source connection as said supply node, and common gates, one of said pair having its source/drain connected to its gate and said control node, and the other of said pair having its source/drain as said output node.
Conveniently said logic gate further comprises an enable transistor connected between said supply node and said supply terminal.
Advantageously each said pull-down transistor is an n FET and said pair of FETs are p FETs.
Advantageously said enable transistor is a p FET.
According to a second aspect of the present invention there is provided a logic gate comprising a current mirror circuit having a supply node, a first node and a second node wherein application of a first current at the first node causes a second current at the second node, plural input pull-down transistors connected between a reference node and one of said first and second nodes, and an output pull-down transistor connected between the other of said first and second nodes, and the reference terminal wherein the supply node has a connection to a supply terminal, the plural input pull-down transistors have respective control terminals connected to a corresponding plurality of input terminals and the output pull-down transistor has circuitry connected to its control node for biasing it on, wherein said input pull-down transistors are mutually substantially identical and said output pull-down transistor is substantially the same as each said input pull-down transistor and the current mirror has a non-unity ratio.
Advantageously at least one input pull-down transistor is connected in series with a second input pull-down transistor.
Conveniently the gate further comprises a disabling transistor connected between said reference node and one of said first and second nodes.
Preferably the gate further comprises an inverter having a circuit output, said inverter being connected to one of said first and second nodes.
REFERENCES:
patent: 4797580 (1989-01-01), Sunter
patent: 4883988 (1989-11-01), Ide et al.
patent: 5039886 (1991-08-01), Nakamura et al.
patent: 05036280 (1993-02-01), None
Chang Daniel D.
Morris James H.
Skrivanek, Jr. Robert A.
STMicroelectronics Limited
Tokar Michael
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