Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-11-03
2002-12-10
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06493848
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to measuring electrical behavior in semi-conductor devices and relates more particularly, to simulating current in MOSFET devices based on an improved barrier model rate equation.
BACKGROUND OF THE INVENTION
The trend in modern semiconductor manufacturing has been to produce semiconductor chips in ever-decreasing sizes. This, in turn, allows electrical components, such as computers, cellular telephones, compact disc players and the like, to be made smaller and more compact as well as faster in operation. The miniaturization of electrical components is deemed to be advantageous in the sale and marketing of the same, since consumers tend to prefer smaller components over similarly priced, yet bulkier models.
In order to achieve this overall miniaturization, it becomes necessary to create smaller versions of the internal elements that make up these electrical components. Much attention has been directed to creating smaller, more densely-packed transistors in order to create, for example, smaller microprocessors as well as other semiconductor chips. In order to design such smaller transistors, it is preferable to be able to model and simulate the behavior of a theoretical design prior to its manufacture.
A semiconductor device, such as a MOSFET, having a source region, a gate region, a drain region and a channel region associated with it, have been successfully modeled in the past. However, as the device is made smaller, the dimensions of these associated regions necessarily decrease. As channel lengths shrink in particular, it has been realized that classical transport concepts, such as drift, diffusion, or other quantities become less reliable. Consequently, the transport equations used to model these devices, and which rely on these factors, are of limited accuracy. Thus they lose their useful in the simulation and design of smaller MOSFETs.
Thus, there is a need to develop an improved model for simulating electrical behavior in semiconductor devices, such as MOSFETs, which provides accurate and useful results, while discounting factors such as electron mobility, diffusion and velocity which become unreliable for modeling in smaller devices.
SUMMARY OF THE INVENTION
The instant invention demonstrates the viability of modeling the current in a short-channel MOSFET without the use of mobility, diffusion or classical electron velocity. Such a model is useful where the uncertainty in the velocity of electrons that traverse the channel becomes comparable to the saturation velocity of electrons in the device. This unfavorable characteristic is present in silicon-based metal-oxide semiconductor field-effect transistors (MOSFETs) currently manufactured. The instant rate-equation model is particularly useful for short-channel MOSFETs, where comparable transport equations have not previously been applied. Results, including current-voltage (I-V) characteristics generated by the instant rate equation (or barrier model), compare well qualitatively to experimental data, as well as to results from electrical device computer simulation programs such as PADRE or SPICE. Furthermore, the instant barrier model replicates features of the current-voltage curve that are often ascribed to variations in the mobility, although mobility is not included in the rate equation.
According to a first aspect of the instant invention, a method for determining a current-voltage characteristic for a semiconductor device having a source region, a drain region and a channel region, comprises: assigning one of a plurality of fixed values to each of at least one of a plurality of model variables including a gate-to-source voltage (V
GS
) to be applied to the device, a drain-to source voltage (V
DS
) to be applied to the device, a first Fermi level (F
1
) corresponding to the source region of the device, a second Fermi level (F
2
) corresponding to the channel region of the device, a width (W) of the channel region, an operating temperature (T) of the device, a quantization energy level (E
qv
) of the device, a height (Vo) of a source-channel barrier of the device, and a mass in a z-direction for electrons in a channel valley (m
zv
); assigning a plurality of differing values for each of the remaining model variables; and determining, for each of the plurality of differing values, a current value (I
12
) from a rate equation modeled after the source-channel barrier. In the above variables, the subscript v denotes a particular valley, and z denotes the direction along the width of the channel.
According to a second aspect of the instant invention, a computer-readable medium encoded with processing instructions is disclosed for implementing a method, performed by a computer, for simulating current-voltage behavior in a semiconductor device having a source region, a channel region and a drain region, the method comprising: receiving an input including one of a plurality of fixed values for each of at least one of a plurality of model variables including a gate-to-source voltage (V
GS
) to be applied to the device, a drain-to source voltage (V
DS
) to be applied to the device, a first Fermi level (F
1
) corresponding to the source region of the device, a second Fermi level (F
2
) corresponding to the channel region of the device, a width (W) of the channel region, an operating temperature (T) of the device, a quantization energy level (E
qv
) of the device, a height (Vo) of a source-channel barrier of the device, and a mass in a z-direction for electrons in a channel valley (m
zv
); assigning a plurality of differing values for each of the remaining model variables; and determining, for each of the plurality of differing values, a current value (I
12
) from a rate equation modeled after the source-channel barrier.
According to a third aspect of the instant invention, an apparatus for simulating current-voltage behavior in a semiconductor device having a source region, a channel region and a drain region, comprises: a processor; a memory connected to the processor, the memory storing a program to control the operation of the processor; and the processor operative with the program to: receive an input including one of a plurality of fixed values for each of at least one of a plurality of model variables including a gate-to-source voltage (V
GS
) to be applied to the device, a drain-to source voltage (V
DS
) to be applied to the device, a first Fermi level (F
1
) corresponding to the source region of the device, a second Fermi level (F
2
) corresponding to the channel region of the device, a width (W) of the channel region, an operating temperature (T) of the device, a quantization energy level (E
qv
) of the device, a height (Vo) of a source-channel barrier of the device, and a mass in the z-direction for electrons in a channel valley (m
zv
); assign a plurality of differing values for each of the remaining model variables; and determine, for each of the plurality of differing values, a current value (I
12
) from a rate equation modeled after the source-channel barrier.
REFERENCES:
patent: 5687355 (1997-11-01), Joardar et al.
patent: 6275059 (2001-08-01), Sah et al.
Agere Systems Guardian Corp.
Levin Naum
Smith Matthew
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