Rate dematching processor

Details Rate dematching processor Rate dematching processor

2007-08-14

2007-08-14

Dildine, R. Stephen (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S800000

Reexamination Certificate

active

10869079

ABSTRACT:
(3n+1)th (n=0, 1, 2, . . . , M/3−1) input data is stored in a first memory102, (3n+2)th (n=0, 1, 2, . . . , M/3−1) input data is stored in a second memory103, and (3n+3)th (n=0, 1, 2, . . . , M/3−1) input data is stored in a third memory104. Information bit, first parity bit, and second parity bit that have been read out by 3 bits are held in an information bit queue108, a first parity bit queue109, and a second parity bit queue110, respectively, to control data supply to the rate dematching circuits111and112by these queues108, 109and110.

REFERENCES:
patent: 2003/0135811 (2003-07-01), Xu et al.
patent: 2004/0187069 (2004-09-01), Pietraski et al.
patent: 2002-9633 (2002-01-01), None
patent: 2002-199048 (2002-07-01), None
patent: 2002-208863 (2002-07-01), None

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