Rapidly testable semiconductor memory device

Details Rapidly testable semiconductor memory device Rapidly testable semiconductor memory device

2005-03-15

2005-03-15

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C365S189070

Reexamination Certificate

active

06868021

ABSTRACT:
A semiconductor memory device has an array of memory cells, an array of sense amplifiers selected at least two at a time by column lines, data bus lines that receive data read from the memory cell array by the selected sense amplifiers, a decision circuit that compares data read by two of the selected sense amplifiers, and an input-output buffer. Normally, the input-output buffer receives and outputs data from one or more of the data bus lines. In a test output mode, the input-output buffer receives and outputs comparison result data from the decision circuit. In a semiconductor memory device with multiple memory cell arrays, this arrangement enables data read from different memory cells in the same memory cell array to be compared, so that redundancy repair can be carried out efficiently.

REFERENCES:
patent: 5621691 (1997-04-01), Park
patent: 5914907 (1999-06-01), Kobayashi et al.
patent: 6269033 (2001-07-01), Ishida et al.
patent: 08-077791 (1996-03-01), None
patent: 2001-35181 (2001-02-01), None

Affiliated with

Also associated with

Rating

Rapidly testable semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Rapidly testable semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Rapidly testable semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3441512