Rapidly reconfigurable FPGA having a multiple region architectur

Details Rapidly reconfigurable FPGA having a multiple region architectur Rapidly reconfigurable FPGA having a multiple region architectur

2000-02-16

2000-11-21

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 38, H03K 19177

Patent

active

06150839&

ABSTRACT:
A field programmable gate array (FPGA) which includes first and second arrays of configurable logic blocks, and first and second configuration cache memories coupled to the first and second arrays of configurable logic blocks, respectively. The first configuration cache memory array can either store values for reconfiguring the first array of configurable logic blocks, or operate as a RAM. Similarly, the second configuration cache array can either store values for reconfiguring the second array of configurable logic blocks, or operate as a RAM. The first configuration cache memory array and the second configuration cache memory array are independently controlled, such that partial reconfiguration of the FPGA can be accomplished. In addition, the second configuration cache memory array can store values for reconfiguring the first (rather than the second) array of configurable logic blocks, thereby providing a second-level reconfiguration cache memory.

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