Rapidly-readable register file

Details Rapidly-readable register file Rapidly-readable register file

1998-08-11

2001-04-17

Pan, Daniel H. (Department: 2171)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C712S022000, C365S189020

Reexamination Certificate

active

06219756

ABSTRACT:

BACKGROUND OF THE INVENTION
1) Field of the Invention
The present invention relates to a register file mounted in a processor such as microprocessor or CPU, and including a plurality of register arrays used for storing intermediate results of a calculation, constants, and so forth. In particular, the present invention relates to a register file having a multiport configuration in which a plurality of read ports and a plurality of write ports are mounted, and a plurality of read accesses and a plurality of write accesses can independently and concurrently be made through these ports.
2) Description of the Related Art
As shown in
FIG. 7
, a register file
100
with a typical multiport configuration includes register arrays
101
forming a word width n (the number of words: for example, n=32, 64, 128, . . . ), and a word having a bit width m (the number of bits: for example, m=16, 32, . . . ) can be stored in each of the register arrays
101
. That is, a main body (register portion) of the register file
100
includes cell arrays arranged in an m by n rectangle.
Further, the register file
100
has three read ports
110
X to
110
Z, and four write ports
120
A to
120
D. Through these ports
110
X to
110
Z and
120
A to
120
D, three read accesses and four write accesses can be made independently and concurrently.
The register file
100
includes read decoders
130
X to
130
Z to respectively decode read addresses Rx to Rz externally input for selections of words to be read from the read ports
110
X to
110
Z. The read decoders
130
X to
130
Z respectively put in a read state the register arrays
101
specified according to results of decoding, and send data (words) stored in the register arrays
101
to the read ports
110
X to
110
Z.
The read ports
110
X to
110
Z are respectively provided with sense amplifiers
111
. Signals read from the register arrays
101
are sent to the sense amplifiers
111
through unillustrated bit lines (data lines). Subsequently, the signals are amplified by the sense amplifiers
111
up to a level at which digital signal processing can be performed.
In addition, the register file
100
includes write decoders
140
A to
140
D to respectively decode write addresses Wa to Wd externally input to specify on which of the register arrays
101
the data input from the write ports
120
A to
120
D should be written. The write decoders
140
A to
140
D respectively put in a write state the register arrays
101
specified according to results of decoding, and the data from the write ports
120
A to
120
D are stored in the register arrays
101
.
Meanwhile, from year to year, higher performance has increasingly been desired in a processor such as microprocessor with the register file incorporated therein. Thus, an operating frequency is made higher and an amount of handled data is increased steadily, thereby increasing the capacity of the register file.
However, in the register file
100
having the configuration as shown in
FIG. 7
, when the number of register arrays
101
is increased up to, for example, 1,028 (1,028 words) so as to increase the amount of handled data, there is a problem in that a delay is caused at a time of read access due to loads on the bit lines extending from the register arrays
101
to the read ports
110
X to
110
Z.
That is, no delay is caused in the register arrays
101
positioned in the vicinity of the sense amplifiers
111
in the read ports
110
X to
110
Z. On the other hand, considerably long physical distances (the lengths of bit lines) are required between the register arrays
101
positioned on the side of the write ports
120
A to
120
D in FIG.
7
and the sense amplifiers
111
.
Hence, it takes a long time to send signals stored in the register arrays
101
at extremely low levels to the sense amplifiers
111
through the bit lines, and amplify the signals by the sense amplifiers
111
, thereafter sending the signals to, for example, flip-flops in the next stage. As a result, the delay may cause a reduction in performance of the whole logic unit.
In view of the facts, as shown in
FIG. 8
, a register file
200
employing a column-row read/write system may be used.
As in the register file
100
shown in
FIG. 7
, the register file
200
shown in
FIG. 8
has n register arrays
201
with a bit width m. However, in the register file
200
, the four register arrays
201
are aligned horizontally (in a lateral direction of FIG.
8
), thereby reducing a word width of the register file
200
to a quarter (n/4) of the word width of the register file
100
. A main body (register portion) of the register file
200
includes cell arrays arranged in an (m by 4) by (n/4) rectangle. That is, the register file
200
is laterally divided into the four columns with the bit width m, and is divided into n/4 rows longitudinally (in a longitudinal direction of FIG.
8
).
Further, the register file
200
has three read ports
210
X to
210
Z, and four write ports
220
A to
220
D. Through these ports
210
X to
210
Z and
220
A to
220
D, three read accesses and four write accesses can be made independently and concurrently.
The register file
200
includes row decoders
230
X to
230
Z and column decoders
231
X to
231
Z to respectively decode read addresses Rx to Rz (which are, for example, 5-bit address information for n=32) externally input for selections of words to be read from the read ports
210
X to
210
Z, and includes 4 to 1 multiplexers
232
X to
232
Z.
Each of the row decoders
230
X to
230
Z selects one specific row from among the n/4 rows depending upon high order bits (for example, three high order bits) in each of the read addresses Rx to Rz, and puts in a read state four register arrays
201
in the row, thereby sending data (words) stored in the register arrays
201
to each of the 4 to 1 multiplexers
232
X to
232
Z.
Each of the column decoders
231
X to
231
Z selects one specific column from among the four columns depending upon low order bits (for example, two low order bits) in each of the read addresses Rx to Rz, thereby sending 4-bit column indicating information to each of the 4 to 1 multiplexers
232
X to
232
Z.
The 4 to 1 multiplexers
232
X to
232
Z respectively free column portions corresponding to the column indicating information from the column decoders
231
X to
231
Z, and send data from the columns to the read ports
210
X to
210
Z.
The read ports
210
X to
210
Z are respectively provided with sense amplifiers
211
identical with those in the above discussion. Signals read from the register arrays
201
are sent to the sense amplifiers
211
through unillustrated bit lines (data lines). Subsequently, the signals are amplified by the sense amplifiers
211
up to a level at which digital signal processing can be performed.
In addition, the register file
200
includes write decoders
240
A to
240
D to respectively decode write addresses Wa to Wd externally input to specify on which of the register arrays
201
the data input from the write ports
220
A to
220
D should be written. The write decoders
240
A to
240
D respectively put in a write state the register arrays
201
specified according to results of decoding (the register array
201
positioned in a predetermined column and a predetermined row), and the data from the write ports
220
A to
220
D are stored in the register arrays
201
.
In the above register file
200
, it is possible to reduce physical distance from the register array
201
to the sense amplifier
211
to, at the longest, a quarter of the longest distance in the register file
100
shown in FIG.
7
. When the register file
200
includes the register arrays
201
to have a capacity of, for example, 1,028 words, the register file
200
has the word width of 256 words, and the physical distance from each of the register arrays
201
to the sense amplifier
211
corresponds to the 256 words at the longest.
Therefore, even when the number of register arrays
201
is increased to increase an amount of handled data, in the register file
200
, it

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