Rapid single-flux-quantum logic circuit and rapid...

Electronic digital logic circuitry – Superconductor – Tunneling device

Reexamination Certificate

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Details

C326S004000, C326S005000, C326S006000

Reexamination Certificate

active

06724216

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to superconductivity circuits, and more particularly to a rapid single-flux-quantum (RSFQ) logic circuit which comprises Josephson junctions and inductance elements.
In the fields of information processing technology and information communication technology, including computer technology, in order to accelerate processing speed further, the logic element which can operate at high speed and by low power consumption is demanded, and a rapid single-flux-quantum logic circuit which is composed of Josephson junctions and inductance elements has been proposed as a logic element which fulfills the high speed and low power consumption demand.
2. Description of the Related Art
FIG.
1
A and
FIG. 1B
show the equivalent circuit and the timing of operation of a RSFQ (rapid single-flux-quantum) circuit by K. K. LIKAREV ET AL., IEEE TRANS. APPL. SUPERCONDUCTIVITY, vol. 1, no. 1, March 1991, which is a conventional typical rapid single-flux-quantum logic circuit.
As shown in FIG.
1
A and
FIG. 1B
, the incoming signals S
1
-Sn are supplied to the RSFQ circuit, various logic operations, such as AND, OR and NOT, are performed, and a pulse logic operation is performed, which outputs a logic output signal Sout synchronized with the timing of a clock signal T supplied to the RSFQ circuit. Since the picosecond SFQ pulse signal is used by the RSFQ circuit as an information carrier, the pulse signal shown in
FIG. 1B
has only the self-sustaining time on the order of picoseconds, and a conventional semiconductor circuit (e.g., an IC circuit) can hardly process the output signal of the RSFQ logic circuit.
For this reason, a direct-connection SFQ/DC voltage converter which combines a direct-current DC voltage converter with the RSFQ circuit of
FIG. 1A
has been proposed.
FIG.
2
A and
FIG. 2B
show the configuration and the waveform of operation of the conventional direct-connection SFQ/DC voltage converter.
As shown in
FIG. 2A
, the conventional direct-connection SFQ/DC voltage converter generally includes a superconductivity circuit including Josephson junctions J
1
-J
6
and inductance elements L
1
-L
5
. The Josephson junctions J
1
-J
4
form an SFQ circuit, and the Josephson junctions J
5
and J
6
form a direct-connection DC voltage converter.
In the SFQ circuit, a first superconducting loop is provided in which the Josephson junctions J
1
and J
3
are connected through the inductance elements L
1
and L
2
and the bias current Ib
1
is supplied to the connection node between the Josephson junction J
1
and the inductance element L
1
. A second superconducting loop is provided in the SFQ circuit in which the input signal T is supplied through the inductance element L
5
to the connection node between the inductance elements L
3
and L
4
. In the second superconducting loop, the Josephson junctions J
2
and J
4
are connected through the inductance elements L
3
and L
4
.
The SFQ circuit produces the output signal F, which is shown in
FIG. 2B
, at the connection node between the Josephson junction J
3
and the Josephson junction J
4
. As previously described with
FIG. 1B
, the output signal F is the picosecond SFQ pulse signal, and a conventional semiconductor circuit can hardly process the output signal of the RSFQ logic circuit.
In the direct-connection SFQ/DC voltage conversion circuit of
FIG. 2A
, the direct-connection DC converter circuit is composed of the Josephson junctions J
5
and J
6
, and the bias current Ib is supplied to the node indicated in FIG.
2
A. The DC converter circuit is connected to the above SFQ circuit at the connection node between the inductance elements L
1
and L
2
. As shown in
FIG. 2B
, the output voltage V of the DC converter circuit is sustained only during the period between the current pulse signal T and the following pulse signal T. This is because the SFQ is held over the period of the pulse in the superconducting loop including the Josephson junctions J
1
and J
3
and the inductance elements L
1
and L
2
.
In the SFQ/DC voltage conversion circuit including the direct-connection DC converter, the DC converter is directly connected to the SFQ circuit, and the circuit design becomes troublesome. When a plurality of SFQ/DC voltage conversion circuits are connected in series in order to obtain a voltage signal on the order that can be processed by the conventional semiconductor circuit, there is a possibility that the respective SFQ circuits are influenced by the corresponding direct-connection DC converters. Usually, it is necessary that a superconducting quantum interference device (SQUID) is connected to each of the SFQ/DC voltage conversion circuits as a subsequent circuit portion. The configuration of such SFQ/DC voltage conversion circuits with the SQUIDs will increase the area of the entire circuit.
FIG. 3
shows a conventional voltage multiplier circuit which is configured by using the plurality of the direct-connection SFQ/DC conversion circuits.
In the voltage multiplier circuit of
FIG. 3
, the SFQ pulse signal is processed by the direct-connection SFQ/DC conversion circuits, and the output of the direct-connection SFQ/DC conversion circuits is further processed by the plurality of the SQUIDs in order to produce the voltage signal on the order that can be processed by the conventional semiconductor circuit.
As shown in
FIG. 3
, the input pulse signal is split into the plurality of pulse signals by the plurality of SFQ pulse splitters SP
1
, SP
2
and SP
3
. The pulse signals output from the SFQ pulse splitters are respectively delivered through the transmission lines T
1
, T
2
, . . . TN. Each of these transmission lines may be formed by either a Josephson transmission line (JTL) or a JTL combined with a buffer circuit. The transmission lines T
1
, T
2
, . . . TN respectively supply the pulse signals of the individual channels CH
1
, CH
2
, . . . CHN to the direct-connection SFQ/DC conversion circuits SFQ/DC-
1
-SFQ/DC-N, respectively.
Furthermore, in the voltage multiplier circuit of
FIG. 3
, the SFQ/DC conversion circuits SFQ/DC-
1
-SFQ/DC-N are connected through the magnetic coupling M to the subsequent circuit portions SQUID
1
-SQUID
N
, respectively. The circuit portions SQUID
1
-SQUID
N
are connected in series, so that the desired output voltage (NxVo) can be produced at the output of one of the circuit portions SQUID
1
-SQUID
N
by the in-series connection of the SQUID
1
-SQUID
N
.
In the voltage multiplier circuit of
FIG. 3
, it is impossible to directly make the in-series connection of the direct-connection SFQ/DC voltage conversion circuits SFQ/DC-
1
-SFQ/DC-N. The desired output voltage (NxVo) can be obtained only by the in-series connection of the SQUID
1
-SQUID
N
.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an improved rapid single-flux-quantum RSFQ logic circuit in which the above-described problems are eliminated.
Another object of the present invention is to provide a rapid single-flux-quantum logic circuit that promotes increasing the flexibility of circuit design.
The above-mentioned objects of the present invention are achieved by a rapid single-flux-quantum RSFQ logic circuit comprising: a first circuit portion which has a first end grounded and has a first Josephson junction and a second Josephson junction which are connected in series; a second circuit portion which has a first end grounded and has a third Josephson junction and a fourth Josephson junction which are connected in series; a first inductance element which connects a second end of the first circuit portion to a second end of the second circuit portion; a tap which is provided in the first inductance element, an input current signal being supplied to the tap; a bias current source which is connected to a first connection node between the first Josephson junction and the second Josephson junction; a second inductance element which connects the first connection node to a second connection node between the third Josephson junction

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