Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1998-01-20
2000-04-04
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 2, 714 3, 714 4, 714 5, 714 20, 714 21, 709713, G06F 9445
Patent
active
060473843
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a computer system having data collection to peripherally units for rapid start-up.
2. Description of the Related Art
Computer systems, in particular telephone exchange systems, need start-up systems (recovery systems) which, when a computer system is being commissioned, or following the occurrence of an alarm, reproduce once more as quickly as possible a state of software and hardware that is suitable for the operation of the computer system. Starting up the computer system is necessary when it is first switched on, when the computer installation program system is changed or following a system failure. In the case of a computer system whose structure comprises a central processor system and peripheral processor systems, the system start-up is controlled by the central processor system of the computer system. The central processor system in this case in particular controls the necessary reloading of the peripheral processor systems with data (code data, control data and so on).
SUMMARY OF THE INVENTION
The present invention provides a computer system which carries out the reloading of the peripheral processor systems as rapidly (and reliably) as possible. Such reloading is necessary when starting up the computer system.
This and other objects and advantages of the invention are achieved by a computer system having a central processor system which controls the computer system centrally, the central processor system including central processors and a common memory connected to the computer system through a bus system, peripheral processor systems which control peripheral units of the computer system, and a recovery system which is contained in the central processor system and which carries out a recovery of the peripheral units by collecting the data to be transferred to the peripheral units for the recovery in the common memory before the transfer of the data, controlling the central processors in such a way that they carry out the collection in parallel fashion.
The parallel collection of the data to be loaded into the peripheral processor systems by all the processors of the central processor system makes rapid start-up of the computer system possible.
A further embodiment of the invention provides that a central processor in each case includes a local memory in which is collected the data to be transferred in advance, before the central processor forwards the data to the common memory. The temporary buffering of the data in the local memories of the central processors achieves a dynamically optimized use of the central memory.
A further embodiment of the invention provides a specific central processor that transfers data into the peripheral units, while the remaining central processors are at the same time collecting further data to be transferred. This configuration further shortens the start-up time of the computer system.
An embodiment of the invention provides that the specific central processor transfers the data to be transferred into the peripheral units using the direct memory access method. This embodiment further shortens the start-up time of the computer system.
An embodiment of the invention provides that the specific central processor transfers the data to be transferred into the periphery in broadcast mode into the periphery. The start-up time is further shortened by the parallel downloading of the data in the broadcast mode.
BRIEF DESCRIPTION OF THE DRAWINGS
In the following text, an exemplary embodiment of the invention is explained in more detail using the drawing, the drawing comprising three figures.
FIG. 1 is a functional block diagram of the hardware structure of an exemplary computer system according to the present invention;
FIG. 2 is a block diagram showing the hardware and software structure of a central processor system; and
FIG. 3 is a block diagram of the hardware components of an exemplary computer system of the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
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Bauer Wolfgang
Puhl Andreas
Ramke Heinz-Werner
Ruppert Karl
Beausoliel, Jr. Robert W.
Bonzo Bryce
Siemens Aktiengesellschaft
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