Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
1999-08-05
2002-05-21
Kim, Kenneth S. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
C712S032000, C712S034000, C712S217000, C712S225000
Reexamination Certificate
active
06393555
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of microprocessors and, more particularly, to the execution of floating point compare operations in a floating point coprocessor.
2. Description of the Related Art
Most microprocessors must support multiple data types. For example, x86-compatible microprocessors must execute two types of instructions; one set defined to operate on integer data types, and a second set defined to operate on floating point data types. In contrast with integers, floating point numbers have fractional components and are typically represented in exponent-significand format. For example, the values 2.15H10
3
and −10.5 are floating point numbers while the numbers −1, 0, and 7 are integers. The term “floating point” is derived from the fact that there is no fixed number of digits before or after the decimal point, i.e., the decimal point can float. Using the same number of bits, the floating point format can represent numbers within a much larger range than integer format. For example, a 32-bit signed integer can represent the integers between −2
31
and 2
31
−1 (using two's complement format). In contrast, a 32-bit (“single precision”) floating point number as defined by the Institute of Electrical and Electronic Engineers (IEEE) Standard 754 has a range (in normalized format) from 2
−126
to 2
127
×(2−2
−23
) in both positive and negative numbers.
FIG. 1
illustrates an exemplary format for an 8-bit integer
100
. As the figure illustrates, negative integers are represented using the two's complement format
106
. To negate an integer, all bits are inverted to obtain the one's complement format
102
. A constant
104
of one is then added to the least significant bit (LSB).
FIG. 2
shows an exemplary format for a floating point value. Value
110
is a 32-bit (single precision) floating point number. Value
110
is represented by a significand
112
(23 bits), a biased exponent
114
(8 bits), and a sign bit
116
. The base for the floating point number (2 in this case) is raised to the power of the exponent and multiplied by the significand to arrive at the number represented. In microprocessors, base
2
is most common. The significand comprises a number of bits used to represent the most significant digits of the number. Typically, the significand comprises one bit to the left of the radix point and the remaining bits to the right of the radix point. A number in this form is said to be “normalized”. In order to save space, in some formats the bit to the left of the radix point, known as the integer bit, is not explicitly stored. Instead, it is implied in the format of the number.
Floating point values may also be represented in 64-bit (double precision) or 80-bit (extended precision) format. As with the single precision format, a double precision format value is represented by a significand (52 bits), a biased exponent (11 bits), and a sign bit. An extended precision format value is represented by a significand (64 bits), a biased exponent (15 bits), and a sign bit. However, unlike the other formats, the significand in extended precision includes an explicit integer bit. Additional information regarding floating point number formats may be obtained in IEEE Standard 754.
The recent increased demand for graphics-intensive applications (e.g., 3D games and virtual reality programs) has placed greater emphasis on a microprocessor's floating point performance. Given the vast amount of software available for x86 microprocessors, there is particularly high demand for x86-compatible microprocessors having high performance floating point units. Thus, microprocessor designers are continually seeking new ways to improve the floating point performance of x86-compatible microprocessors.
One technique used by microprocessor designers to improve the performance of all floating point instructions is pipelining. In a pipelined microprocessor, the microprocessor begins executing a second instruction before the first has been completed. Thus, several instructions are in the pipeline simultaneously, each at a different processing stage. The pipeline is divided into a number of pipeline stages, and each stage can execute its operation concurrently with the other stages. When a stage completes an operation, it passes the result to the next stage in the pipeline and fetches the next operation from the preceding stage. The final results of each instruction emerge at the end of the pipeline in rapid succession.
Another popular technique used to improve floating point performance is out-of-order execution. Out-of-order execution involves reordering the instructions being executed (to the extent allowed by dependencies) so as to keep as many of the microprocessor's floating point execution units as busy as possible. As us ed herein, a microprocessor may have a number of execution units (also called functional units), each optimized to perform a particular task or set of tasks. For example, one execution unit may be optimized to perform integer addition, while another execution unit may be configured to perform floating point addition.
Typical pipeline stages in a modem microprocessor include fetching, decoding, address generation, scheduling, execution, and retiring. Fetching entails loading the instruction from the instruction cache. Decoding involves examining the fetched instruction to determine how large it is, whether or not it requires an access to memory to read data for execution, etc. Address generation involves calculating memory addresses for instructions that access memory. Scheduling involves the task of determining which instructions are available to be executed and then conveying those instructions and their associated data to the appropriate execution units. The execution stage actually executes the instructions based on information provided by the earlier stages. After the instruction is executed, the results produced are written back either to an internal register or the system memory during the retire stage.
Yet another method used by designers to improve performance and simplify the design of the microprocessor is to logically separate the floating point portions of the microprocessor from the integer portions. In this configuration, the floating point portions of the microprocessor are referred to as a floating point coprocessor or floating point unit (FPU), even though it is typically implement ed on the same silicon substrate as the microprocessor. If a floating point instruction is detected by the microprocessor, the instruction is handed off to the floating point coprocessor for execution. The coprocessor then executes the instruction independently from the rest of the microprocessor. Since the floating point coprocessor has its own set of registers, this technique works well for most floating point instructions. However, there are some floating point instructions that interface with the integer side of the microprocessor. For example, the instructions FCOMI, FCOMIP, FUCOMI, and FUCOMIP (collectively referred to herein as “FCOMI-type” instructions) perform floating point compare operations and then set certain integer flags (i.e., flags in the integer EFLAGS register). After executing FCOMI-type instructions, the coprocessor is configured to convey the results to the integer portions of the microprocessor for storage in the EFLAGS register. The extra step of conveying the results to the integer side for storage normally does not inhibit performance significantly.
However, in many cases FCOMI-type instructions are followed by FCMOV (floating point conditional move) type instructions. As used herein, FCMOV-type instructions include all floating point instructions that perform conditional moves based upon one or more integer flags. FCMOV-type instructions test the flags in the EFLAGS register and then perform a move operation if a specified test condition is true (e.g., if the zero flag is set). The FCMOV-type instruction is depende
Juffa Norbert
Meier Stephan G.
Oberman Stuart F.
Weber Frederick D.
Advanced Micro Devices , Inc.
Conley Rose & Tayon PC
Kim Kenneth S.
Kivlin B. Noäl
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