Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2007-01-30
2010-11-23
Bragdon, Reginald G (Department: 2189)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S200000, C711S220000, C711SE12002
Reexamination Certificate
active
07840744
ABSTRACT:
In an aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) generating a first command and associated address of a first type that does not indicate a rank of memory targeted by the first command; (2) determining whether the memory includes a plurality of ranks; (3) if the memory includes a plurality of ranks, employing the processor to update the address associated with the first command to indicate a memory rank targeted by the first command; (4) if the memory does not include a plurality of ranks, employing the processor to update the address associated with the first command to indicate the memory does not include a plurality of ranks; and (5) converting the first command and associated updated address to a second command and associated address that are employed to access the memory. Numerous other aspects are provided.
REFERENCES:
patent: 6961281 (2005-11-01), Wong et al.
patent: 2007/0192563 (2007-08-01), Rajan et al.
Bellows Mark David
Haselhorst Kent Harold
Irish John David
Norgaard David Alan
Bragdon Reginald G
Dugan & Dugan PC
International Business Machines - Corporation
Mackall Larry T
Nock James R.
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