Range selectable address decoder and frame memory device for...

Details Range selectable address decoder and frame memory device for... Range selectable address decoder and frame memory device for...

2006-03-07

2006-03-07

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including specified plural element logic arrangement

C365S230060

Reexamination Certificate

active

07009893

ABSTRACT:
A frame memory device capable of processing graphic data at high speed so as to reduce a burden to be imposed on a processor in a portable terminal of a limited size is disclosed. The frame memory device includes a number of memory cells aligned in a matrix form, and range selectable row/column address decoders capable of designating row/column addresses of a desired range by two addresses, to thereby select a number of memory cells of a desired range all at a time and write data in the selected memory cells.

REFERENCES:
patent: 5036493 (1991-07-01), Nielsen
patent: 5208781 (1993-05-01), Matsushima
patent: 5999480 (1999-12-01), Ong et al.
patent: 6026046 (2000-02-01), Larson
patent: 6671210 (2003-12-01), Watanabe et al.

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