Random message verification technique

Details Random message verification technique Random message verification technique

1999-09-29

2003-05-06

Beausoliel, Robert (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S736000, C324S701000, C348S184000

Reexamination Certificate

active

06560724

ABSTRACT:

CROSS REFERENCE TO CO-PENDING APPLICATIONS
None.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to digital data processing systems and more particularly to techniques for testing access to a shared resource having a plurality of resource requesters.
2. Description of the Prior Art
The earliest computer systems generally employed a single processor, single memory, and single peripheral equipments of various rudimentary types. As systems became more complex, additional peripherals were added, prompting some switching functions provided by an input/output controller. Further complexities produced systems having multiple memory modules. Oftentimes, multiple computers were coupled together to perform larger tasks which could be parsed into two or more parallel functions. By providing for peripheral sharing and intercomputer input/output, such multiple computer systems became primitive multiple processor systems.
Today, even the simplest forms of general purpose computers have some modularity permitting customization through the addition of memories, input/output channels, etc. The most complex of current day computers employ multiple processors which share multiple memories, input/output controllers, and other resources.
Testing of early computers involves determining whether the various components function as intended. Does the processor properly execute each defined instruction? Does the memory properly store data? Do each of he input/output devices function as specified?
Similarly, testing of large modem multiprocessor systems requires exercising each of the components to ascertain that each module functions as intended. However, even though this type of testing is necessary, it is not sufficient. Because of the multiple user/multiple shared resource environment, substantial testing of intercomponent communication is also required. Not only is it important to verify that each user can properly communicate with each resource, it is absolutely necessary to show that all users can communicate with all resources, as simultaneously as permitted by the priority scheme.
This type of testing becomes very complex, because it needs to randomly (or pseudo-randomly) perform functional testing and assessment from the perspective of multiple users and multiple resources. In the past, this has necessitated specialized test equipment driven by laboriously defined test patterns followed by time consuming manual analysis of the results.
SUMMARY OF THE INVENTION
The present invention overcomes many of the disadvantages found within the prior art by providing apparatus for and a method of testing intercomponent communication within a multiple user/multiple shared resource environment. In accordance with the technique of the present invention, intercomponent test messages are automatically generated consistent with a predefined format. The test messages are randomly transferred by the various different requesters to a shared resource. The present invention automatically verifies the responses received by the requesters from the shared resource.
Though the present invention is applicable to a general class of situations, the preferred mode is practiced within a Horizon mainframe computer system available from Unisys Corporation. In this system, the main memory storage unit is accessible by up to four asynchronous and independent ports. These ports serve as requesters on behalf of instruction processors, input/output processors, and other users. In ordinary operation, a port transmits a message to the main memory storage unit which specifies the requested service. The main memory storage unit decodes the message and honors the enclosed request in accordance with a predefined priority scheme. After honoring the request, the results are formatted as a message which is transferred to the port specified in the request.
The apparatus of the preferred mode of the present invention, generates test messages to be randomly transferred to the main memory storage unit by each of the available ports. As messages are received by the various ports from the main memory storage unit in response to the test messages, these responses are verified for proper operation and routing. Each of the requesters has counters which are incremented in a predefined fashion to provide uniqueness of the test messages within the sequence. Corresponding counters within the requesters permit the receiving requesters to create the anticipated response messages to enable verification. The present invention is structured to continuously generate test messages and verify responses until testing is terminated by the operator. A special error signal is produced whenever an unexpected response message is received.


REFERENCES:
patent: 5652908 (1997-07-01), Douglas et al.
patent: 5737518 (1998-04-01), Grover et al.
patent: 6195765 (2001-02-01), Kislanko et al.
patent: 6401223 (2002-06-01), DePenning

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