Random access multiport memory capable of simultaneously accessi

Static information storage and retrieval – Addressing – Multiple port access

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36523006, 36518904, G11C 800

Patent

active

057176469

ABSTRACT:
A random access multiport memory includes a plurality of interface ports, a read/write control logic and a random access memory. Each interface port consists of an address bus, a data input/output bus, a read input signal and a write input signal. The read/write control logic consists of a plurality of address decoders, an input control logic and an output control logic. This random access multiport memory provides the capability that each addressable memory location can be directly, independently and randomly read or write by the plurality of ports.

REFERENCES:
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patent: 4930066 (1990-05-01), Yokota
patent: 5201037 (1993-04-01), Kohiyama et al.
patent: 5247637 (1993-09-01), Leedom et al.
patent: 5530836 (1996-06-01), Busch et al.
patent: 5542067 (1996-07-01), Chappell et al.

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