Random access MOS memory cell using double level polysilicon

Details Random access MOS memory cell using double level polysilicon Random access MOS memory cell using double level polysilicon

1980-09-30

1984-08-21

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Capacitors

357 23, 365182, G11C 1140, G11C 1124

Patent

active

044674503

ABSTRACT:
A cell design for an MOS random access memory is disclosed. Two levels of polycrystalline silicon are used, one for the bias voltage side of the storage capacitors and another for the gates of the MOS transistors and as the bit select line or to connect the gates to the bit select line. The bit select or X address line may overlie both the first and/or second level poly, so space is saved in the cell layout. A "V-groove" anisotropically etched storage capacitor may include the MOS access transistor in one end, formed by double implant.

REFERENCES:
patent: 4012757 (1977-03-01), Koo

Affiliated with

Also associated with

Rating

Random access MOS memory cell using double level polysilicon does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Random access MOS memory cell using double level polysilicon, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Random access MOS memory cell using double level polysilicon will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1938678