Random access memory with circuitry for concurrently and sequent

Details Random access memory with circuitry for concurrently and sequent Random access memory with circuitry for concurrently and sequent

1994-11-04

1996-04-30

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

365221, 36523005, 36523006, 365239, 365233, G11C 700

Patent

active

055131395

ABSTRACT:
A memory system includes a memory array of cells arranged in "r" rows and "c" columns, with each row of cells connected to a write conductor and to a separate read conductor. The memory array may be simultaneously written into and read from by a write address decoder having "r" outputs, one output connected to and corresponding to each write conductor and a read address decoder having "r" outputs, one output connected to and corresponding to each read conductor. Control signals are applied to the write address decoder to cause the outputs of the write address decoder to scan the memory array at a first rate, in sequence, in a first direction, and control signals are applied to the read address decoder to cause the outputs of the read address decoder to scan the memory array at a second rate, in sequence, in a second direction, opposite the first direction. The first and second rates and the number of rows of the memory array are selected such that no memory location is written into and read from during the same time interval, preventing interference between the read and write functions.

REFERENCES:
patent: 4777636 (1988-10-01), Yamashita et al.
patent: 5255220 (1993-10-01), Filliman
patent: 5265049 (1993-11-01), Takasugi

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