Random access memory system with circuitry for avoiding use of d

Details Random access memory system with circuitry for avoiding use of d Random access memory system with circuitry for avoiding use of d

1987-08-12

1989-09-19

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Bad bit

365195, 365236, 365219, 371 7, 371 101, 371 111, G11C 700, G11C 2900

Patent

active

048687898

DESCRIPTION:

BRIEF SUMMARY
A major problem in the semiconductor industry is the occurrence of faults in integrated circuits. The larger the scale of integration, the more serious the problem. It is common practice to test chips and discard those which are faulty. This becomes very wasteful when the scale of integration is large because so many chips suffer defects that the manufacturing yield becomes unacceptably low. For this reason alternative techniques have been developed, especially in the case of integrated circuit memories. It is well known to provide redundant memory cells which can be used to replace defective cells in a manner which is transparent to the user of the memory. Disadvantages of this approach are the additional chip area occupied by the redundant cells and associated circuitry and the need to customise every defective chip individually after it has been tested to locate faulty cells.
A more specific problem which arises with dynamic RAM chips is a kind of graceful degradation as the refresh interval is increased. Long refresh intervals are very desirable because they reduce the power consumption of dynamic RAM but, as the interval is increased it is found that randomly located cells begin to fail one by one.
When integrated circuits are diced into individual chips it is always possible at the last resort to discard defective chips and it is also possible to grade the chips into different speeds. These possibilities are not available in the case of wafer scale integration and alternative techniques have had to be devised. These include an extension of the redundancy approach whereby discretionary wiring is utilised to connect into the wafer only the functional modules thereof. The modules of a wafer scale integrated circuit may be equated with undiced chips. An alternative approach which was disclosed originally in U.S. Pat. No. 3,913,072 utilises modules which incorporate configuration logic and can be commanded to grow a chain of good modules. A reiterated test and growth procedure rejects defective modules and adds good modules one by one to the chain. This has the great advantage that no expensive customising of the wafer scale circuit is needed. The chain of good modules is grown under software control and it is readily possible to grow the chain afresh every time the circuit is powered. Equally, it is possible to store information defining the commands which are used in growing a good chain, e.g. in an ROM on the wafer or off the wafer or in external storage such as a disc. The technique of this prior art is nevertheless only a partial solution. Any modules which are excluded from the chain represent wasted silicon area. If the modules themselves are complex, there is a significant risk that a large proportion of modules will suffer from defects. Moreover, the larger the number of defective modules, the less efficient is the chain growing process. The efficiency may be defined as the proportion of modules which are good which are actually incorporated in the chain. If the chain is forced to avoid a significant proportion of bad modules, it will also fail to include significant numbers of good modules.
In systems wherein configuration logic is commanded to grow the modules into a long chain (often called a spiral because of a typical growth pattern) which avoids defective modules, a simple bus structure is essential; otherwise the configuration logic has to switch too many connections. In proposals of this kind, e.g. U.S. Pat. No. 3,913,072, shift registers have been contemplated as the memory devices. The chain of modules becomes a very large shift register. A disadvantage of such an arrangement is the long average latency in accessing data. Another disadvantage is that any fault in a shift register corrupts all data. For this reason it is already known in large scale integrated circuits to use a random-access memory (RAM) addressed by a free-running address counter as a replacement for a large shift register. RAM faults only affect data locally.
If the known redundant cell techniques were to be applied to

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Aubusson et al, IEEE Journal of Solid-State Circuits, vol. SC-13, No. 3, Jun. 1978, "Wafer-Scale Integration-A Fault Tolerant Procedure", pp. 339-344.

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