Random access memory system having high-speed serial data paths

Details Random access memory system having high-speed serial data paths Random access memory system having high-speed serial data paths

1981-01-19

1983-10-25

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Serial read/write

365205, 365240, G11C 700, G11C 800

Patent

active

044123132

ABSTRACT:
To substantially increase the bandwidth of a random access memory (RAM), a shift register is disposed within the memory array such that the shift register lies parallel to the word lines and is connected to at least individual ones of the bit lines contained within the array. Separate high-speed serial input and output lines are provided by the shift register. These lines are in addition to and operate independently of the slower speed input and output lines normally provided by the RAM. Through this arrangement, a row of data can be transferred to and from the memory array at a rate substantially faster than the single-bit access rate of the RAM.

REFERENCES:
patent: 3763480 (1973-10-01), Weimer
patent: 4044339 (1977-08-01), Berg
patent: 4106109 (1978-08-01), Fassbender
patent: 4120048 (1978-10-01), Fuhrman
patent: 4144590 (1979-03-01), Kitagawa et al.
patent: 4330852 (1982-05-01), Redwine et al.
patent: 4347587 (1982-08-01), Rao
Proebsting, "Dynamic MOS RAMS Technology", 1979 Mostek Memory Data Book and Designers Guide, 3/79, pp. 233-238.

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