Random access memory redundancy circuit employing fusible links

Details Random access memory redundancy circuit employing fusible links Random access memory redundancy circuit employing fusible links

1995-06-13

1996-07-02

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

365 51, 3652257, G11C 700, G11C 2900

Patent

active

055329667

ABSTRACT:
A semiconductor random access memory (RAM) is disclosed having a number of array blocks (14), each array block (14) including standard rows, standard columns, redundant rows (24) and redundant columns (26). A row redundancy circuit (44) is provided for each array block that includes a single row fuse bank (28). Within the row fuse bank (28) are row disable fuses (42) and redundant row fuses (54) interspersed at regular intervals between the row disable fuses (42). Each row disable fuse (42) disables a standard row segment (32) when opened. A redundant row segment (46) is driven according to the combination of opened redundant row fuses (54). A column redundancy circuit (62) includes a number of column fuses (64) disposed in a column fuse bank (30). Redundant columns (26) are enabled by opening selected ones of the column fuses (64). If a redundant column (26) is driven the remaining standard columns of its associated array block (14) are disabled. Column fuse banks (30) are commonly aligned with row fuse banks (28) along fuse axes (16 and 18).

REFERENCES:
patent: 4228528 (1980-10-01), Cenker et al.
patent: 5270976 (1993-12-01), Tran
patent: 5323348 (1994-06-01), Mori
patent: 5377146 (1994-12-01), Reddy et al.
patent: 5430679 (1995-07-01), Hiltebeitel

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