Random access memory (RAM) method of operation and device...

Details Random access memory (RAM) method of operation and device... Random access memory (RAM) method of operation and device...

2005-04-12

2005-04-12

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Read/write circuit

C365S189030

Reexamination Certificate

active

06879523

ABSTRACT:
A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM device (102) and memory device (104) may be connected to one another by point-to-point unidirectional connections. Command data issued by a device, such as a network processing unit (NPU) (110), can flow through all devices beginning with a CAM device (102) and eventually to a memory device (104). A memory device (104) can compare its own current result data with that of a previous device in a flow (such as another RAM device), and generate an output response.

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“IEEE Standard for Scalable Coherent Interface (SCI)”,IEEE Std 1596-1992, Institute of Electrical and Electronic Engineers, Inc., New York, NY, pp. 4-25 and 47-72, May 23, 2001.

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