Random access memory including selective activation of...

Static information storage and retrieval – Read/write circuit – Signals

Reexamination Certificate

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C365S230060, C365S200000

Reexamination Certificate

active

11065196

ABSTRACT:
A random access memory that includes an array of memory cells, a first circuit configured to receive an address to address memory cells in the array of memory cells, and a second circuit. The second circuit is configured to obtain control signals including an address strobe signal and gate the address strobe signal using other control signals to provide a gated address strobe signal and to control activation of a select line signal based on the gated address strobe signal.

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patent: 6343352 (2002-01-01), Davis et al.
patent: 2002/0046331 (2002-04-01), Davis et al.

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