Random access memory having separate read out and write in bus l

Details Random access memory having separate read out and write in bus l Random access memory having separate read out and write in bus l

1988-11-08

1990-09-04

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Differential sensing

365190, 36518901, 365154, 307530, G11C 700, G11C 1140

Patent

active

049549928

ABSTRACT:
A dynamic random access memory device includes a pair of write-in data transferring buses for transferring data to be written, a pair of read-out data transferring buses for transferring data to be read provided additionally and separately from the write-in data transferring bus pair and a plurality of current mirror type sense amplifiers formed of CMOS transistors and each amplifier being provided between a bit line pair and the read-out data transferring bus pair and having input nodes connected to the corresponding bit line pair and the read-out data transferring bus pair forming output nodes thereof. The current mirror type sense amplifiers of CMOS transistors are activated in response to an output of a column decoder at earlier time than the time when conventional flip-flop type sense amplifiers are activated.

REFERENCES:
patent: 3940747 (1976-02-01), Kuo et al.
patent: 4044340 (1977-08-01), Itoh
patent: 4509147 (1985-04-01), Tanimura et al.
patent: 4724344 (1988-02-01), Watanabe
patent: 4791324 (1988-12-01), Hodapp
patent: 4803663 (1989-02-01), Miyamoto et al.
patent: 4843595 (1989-06-01), Suzuki
patent: 4845672 (1989-07-01), Waterabe et al.
'87 VLSI Symposium, Digest of Tech. Papers: "BICMOS Circuit Technology for High Speed Drams", by S. Watanabe et al, 1987, pp. 79-80.

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