Random access memory having selective intra-bank fast activation

Details Random access memory having selective intra-bank fast activation Random access memory having selective intra-bank fast activation

1996-06-26

1997-09-23

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365207, 36523003, G11C 700

Patent

active

056711883

ABSTRACT:
A dynamic random access memory (DRAM) (10) is disclosed. Memory cell arrays (12) within the DRAM have word lines and bit lines, the bit lines being logically divided into bit line sections (26a-p). Corresponding to each bit line section (26a-p) is a sense/decode section (28a-p) having a fast and slow sense mode of operation. When data are read from a particular bit line section (26a-p) the corresponding sense decode section (28a-p) operates in the fast sense mode while the remaining sense/decode sections (28a-p) operate in the slow sense mode, providing for lower power consumption and/or faster access speeds.

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