Random access memory device operable in a normal mode and in a t

Details Random access memory device operable in a normal mode and in a t Random access memory device operable in a normal mode and in a t

1987-07-24

1989-10-10

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

365201, 36523003, 36518904, G11C 700, G11C 1140

Patent

active

048736694

ABSTRACT:
A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switches are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected to one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.

REFERENCES:
patent: 4464750 (1984-08-01), Tatematsu
patent: 4672582 (1987-06-01), Nishimuru et al.
patent: 4742486 (1988-05-01), Takemae
patent: 4744061 (1988-05-01), Takemae et al.
"A Reliable 1-M bit DRAM with a Multi-Bit-Test Mode", Kumanoya, et al., IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, Oct., 1985, pp. 909-913.

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