Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1985-11-18
1988-07-19
Moffitt, James W.
Static information storage and retrieval
Read/write circuit
Data refresh
365230, G11C 800
Patent
active
047589930
ABSTRACT:
A dynamic random access memory (DRAM) device is formed on a semiconductor substrate, the device having an array of memory cells which are divided in several sub-arrays. The device has memory blocks each containing one of the sub-arrays, a word decoder and column decoder. Each of the memory blocks is selected independently to perform an access operation and refresh operation. As long as different memory blocks are selected for the respective operations, both operations are performed in parallel, however, when the same memory block is selected for both operations, namely, double selection, a comparison circuit detects the double selection and gives priority to one of the operations. The operation selected thus, preferentially performed. Usually, the refresh operations is then performed. However, in order to decrease the "busy ratio" of the device, the access operation is performed preferentially. Further, a complicated operation for priority selection may be performed according to a predetermined schedule memorized in a priority providing means. In addition, a common word bus line is proposed for accessing each of the memory blocks, namely, each sub-arrays, in order to reduce the number of common word lines for realizing a further high packing denisty of the DRAM device. This common bus line is also applicable to other devices such as a static RAM.
REFERENCES:
patent: 3810129 (1974-05-01), Behman et al.
patent: 4106108 (1978-08-01), Cislaghi
patent: 4112513 (1978-09-01), Elsner
Fujitsu Limited
Moffitt James W.
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