Random access memory cell with implanted capacitor region

Details Random access memory cell with implanted capacitor region Random access memory cell with implanted capacitor region

1988-06-21

1989-05-02

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Capacitors

365182, 365184, 357236, 357 41, 357 51, 357 91, G11C 1124, G11C 1134, H01L 2978, H01L 2702

Patent

active

048274488

ABSTRACT:
An N-channel MOS random access memory of the one transistor type is disclosed. The cell utilizes an ion implanted area beneath the capacitor dielectric to permit lower bias voltages on the capacitor. In one example, two levels of polycrystalline silicon are used, one for the bias voltage side of the storage capacitor, and the other for the gate of the MOS transistor and to connect the gate to the bit select line. The capacitor dielectric may be formed of thermal silicon oxide which is about half as thick as the gate insulator of the MOS transistor in the cell. In another example, a single-level poly cell uses an implanted region for the same purpose; the capacitor dielectric is the same thickness as the MOS gate insulator so the lower bias voltage functions to reduce stress failures of the dielectric.

REFERENCES:
patent: 3811076 (1974-05-01), Smith, Jr.
patent: 3834959 (1972-06-01), Dennard et al.
patent: 4012757 (1977-03-01), Koo
patent: 4240092 (1980-12-01), Kuo
patent: 4319342 (1982-03-01), Scheuerlein
patent: 4371955 (1983-02-01), Sasaki
patent: 4502208 (1985-03-01), McPherson
patent: 4574465 (1986-03-01), Rao
patent: 4592022 (1986-05-01), Shimohigashi et al.

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