Random access memory cell

Details Random access memory cell Random access memory cell

2001-02-12

2001-11-27

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S174000, C365S177000, C365S182000, C365S185040, C365S185150, C365S185240, C365S185260, C365S185050

Reexamination Certificate

active

06324092

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90100098, filed Jan. 3, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a type of memory cell. More particularly, the present invention relates to a random access memory cell.
2. Description of Related Art
In general, random access memory (RAM) can be categorized into two major types: dynamic random access memory (DRAM) and static random access memory (SRAM). Because the process of reading data from a DRAM cell is a destructive operation, meaning that data originally held inside the memory cell is destroyed after the reading, constant refreshing of memory cell data is required. In addition, since the DRAM cell uses a capacitor to store up the charges for representing data, the capacitor should be sufficiently large to prevent data loss. In reality, each memory cell should be made as small as possible in order to cram more devices within a chip. The reduction of each memory cell and hence the capacitor inside the cell means that only a very small voltage and current can be provided. However, the provision of a small voltage or current renders the probing of any voltage or current changes difficult. Ultimately, operating speed of the memory cell is reduced.
On the other hand, the process of reading data from a SRAM cell is non-destructive. There is no need to perform frequent data-refreshing operations. However, each SRAM cell consists of a minimum of four MOS transistors. Therefore, each SRAM cell occupies a volume much greater than a DRAM cell.
In brief, a conventional memory cell has at least the following drawbacks, including:
1. For DRAM, frequent refresh of memory DRAM cell data is required because the data inside the cell is destroyed after each reading operation.
2. Since a capacitor is used to store data charges in DRAM but only a small capacitor can be produced due to miniaturization, very small voltage or current can be provided.
3. A SRAM cell consists of at least four MOS transistors. Hence, each SRAM cell needs to occupy a much larger volume than a DRAM cell.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a random access memory cell having a unit cell volume much smaller than a static random access memory (SRAM) cell and employing a non-destructive reading process. Moreover, the RAM cell provides a reading current much greater than a conventional dynamic random access memory (DRAM) cell so that a higher operating speed can be attained.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a random access memory (RAM) cell. The RAM cell includes a first transistor and a second transistor. A control gate of the first transistor is coupled to a control signal line. A data read terminal of the first transistor is coupled to a data read line. An earth terminal of the first transistor is connected to a ground. A floating gate terminal of the first transistor is located between a portion of a substrate and a portion of the control gate. A control gate of the second transistor is also coupled to the control signal line. The data write terminal of the second transistor is a data write line. A data transmission terminal of the second transistor is coupled to the floating gate of the first transistor. To write data into the RAM cell, a write control voltage is applied to the control signal line. Similarly, to read data from the RAM cell, a read control voltage is applied to the control signal line. The write control voltage is greater than the read control voltage.
In summary, this invention utilizes a floating gate to store data charges. Since the stored data are not destroyed after each data reading operation, frequent data refreshing is not required. In addition, this invention uses only 2.5 conventional transistors. Hence, each RAM cell occupies a volume much smaller than a SRAM cell.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5757700 (1998-05-01), Kobayashi
patent: 5867443 (1999-02-01), Linderman
patent: 6075738 (2000-06-01), Takano
patent: 6094368 (2000-07-01), Ching
patent: 6198652 (2001-03-01), Kawakeibo et al.
patent: 6198682 (2001-03-01), Proebsting
patent: 6240032 (2001-05-01), Fukumoto

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