Random access memory cell

Details Random access memory cell Random access memory cell

1983-01-17

1984-06-19

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Flip-flop

365174, G11C 1140

Patent

active

044556250

ABSTRACT:
Two memory cells each can be entirely fabricated in only two isolation beds. In one embodiment each bed contains one lateral PNP and one vertical NPN transistor in a merged structure. To obtain faster switching speeds, the PNP transistors are cross-coupled as flip-flop transistors while the NPN transistors act as load transistors. A word select signal is applied to forward bias the base-emitter junctions of the NPN load transistors, to thereby generate a potential difference between bit lines coupled to the emitters of the PNP flip-flop transistors.

REFERENCES:
patent: 3535699 (1970-10-01), Gaensslen et al.
patent: 3969708 (1976-07-01), Sonoda
W. Baitinger et al., "MOS FET Storage Cell," IBM Tech. Discl. Bull., vol. 13, No. 10, Mar. 1971, p. 3160.

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