Random access memory

Details Random access memory Random access memory

2000-07-07

2002-04-02

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including specified plural element logic arrangement

C365S154000, C365S190000

Reexamination Certificate

active

06366504

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention relates to static random access memories (SRAM).
2. Description of the Prior art
A static random access memory comprises a matrix formed of columns and rows of memory cells. The rows of cells can be addressed by an address decoder. Each column is read/written using a direct bit line and an inverted bit line.
To perform a read cycle in SRAM the bit lines must be at a predetermined logic level, in other words they must be either charged or discharged, as appropriate. As their inherent capacitance is high, charging or discharging them takes some time and the duration of a read cycle is therefore long. Also, the power consumption of the memory is relatively high.
To reduce these drawbacks it is already known in the art to divide at least one of the bit lines into a plurality of sections connected to respective inputs of an output logic gate. See U.S. Pat. No. 5,729,501, for example.
In this way it is possible to reduce the capacitance of the bit lines and thereby save power on each write or read operation.
The object of the invention is to improve on prior art memories by proposing a memory with even lower power consumption and with more favorable transistor dimensions.
SUMMARY OF THE INVENTION
The invention therefore provides a random access memory comprising a matrix made up of cells arranged in rows and columns and in which the cells are adapted to be addressed row by row, each cell of a row is connected to first and second bit lines, and at least the first bit line is subdivided into a plurality of sections connected to respective inputs of an output logic gate, which memory includes read/write control means adapted to apply the following logic functions to each of the first and second bit lines directly or indirectly and selectively, according to whether a required operation is a write or a read.
Sel.((W.D) or {overscore (W)})) is applied to the first bit line, whilst Sel.W.D is applied to both the first and second bits lines, where “Sel” is a cell selection signal representative of the address, “W” is the write command, {overscore (W)} is a read command, “D” is the data to be written into the addressed cell and “.” indicates the AND function.
Other features and advantages of the invention will become apparent in the course of the following description, which is given by way of example only and with reference to the accompanying drawings.


REFERENCES:
patent: 5729501 (1998-03-01), Phillips et al.
patent: 5850367 (1998-12-01), Wada et al.
patent: 5901079 (1999-05-01), Chiu et al.
patent: 6212094 (2001-04-01), Rimondi
patent: 6240009 (2001-05-01), Naffziger et al.
“0.5&mgr;m 2M-Transistor BiPNMOS Channelless Gate Array”, Hara et al., IEEE Journal of Solid-Stae Circuits 26 (1991 (Nov. ), No. 11, New York.

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