Static information storage and retrieval – Read/write circuit – Noise suppression
Patent
1976-05-26
1978-04-18
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Noise suppression
307238, 365203, G11C 702
Patent
active
040854582
ABSTRACT:
In a n-channel (or p-channel) random access memory in which a plurality of memory cells are arranged in a matrix form in a p-type (or n-type) semiconductor substrate, clamping MOSFET's are connected between word lines provided for the associated rows of memory cells of the matrix and a reference potential to which gates the source electrodes of the information storing MOSFET's of the memory cells are connected. The clamping MOSFET has a lower threshold voltage than a row selecting MOSFET connected to the word line and clamps the word line when the word line is not selected, so that a delay in the read-out operation is eliminated or suppressed.
REFERENCES:
patent: 3980899 (1976-09-01), Shimada et al.
Ikuzaki Kunihiko
Ishihara Masamichi
Ito Tsuneo
Sato Takashi
Hecker Stuart N.
Hitachi , Ltd.
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