Random access memories (RAM) and more particularly to self-timed

Details Random access memories (RAM) and more particularly to self-timed Random access memories (RAM) and more particularly to self-timed

1992-08-24

1994-06-28

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Differential sensing

36518908, 365201, 365203, 365195, G11C 702

Patent

active

053253370

ABSTRACT:
A self-timed RAM (2) having a two-phase read and write operating cycles which comprise a precharge phase and a discharge phase and which is clocked by a clock signal. The self-timed RAM comprises control means (18, 20, 24, 22, 26, 28, 30) for initiating and controlling the precharge phase followed by the discharge phase in response to a first transition of the clock signal. The self-timed RAM further comprises logic means (30, ERRFLG) which determines when either phase of the two-phase operating cycle has not been completed before the next first transition of the clock signal and in response thereto activates an error indicating means (ERRFLG) to indicate that an error may have occurred during the RAM operating cycle. A controlling system of the RAM can then determine that an error may have occurred during the RAM operating cycle by checking the error indicating means (ERRFLG).

REFERENCES:
patent: 4627032 (1986-12-01), Kolwicz et al.

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