Random access-erasable read only memory cell

Details Random access-erasable read only memory cell Random access-erasable read only memory cell

1976-03-04

1978-06-13

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Flip-flop

307279, 365184, G11C 1140, G11C 1700

Patent

active

040952819

ABSTRACT:
Transistor memory cells which may be operated in both the erasable "read only" and the "random access" modes. Each cell includes a plurality of MOS transistors interconnected to permit random access storage and at least two MNOS transistors. The latter may be set, one to one threshold level and the other to a second threshold level to represent read only storage of a logic 1, and the threshold levels may be reversed to represent read only storage of a logic 0. The MOS transistors may be randomly accessed both for read and write independently of what the MNOS transistors are storing.

REFERENCES:
patent: 3493786 (1970-02-01), Ahrens et al.
patent: 3636530 (1972-01-01), Mark et al.
patent: 3662351 (1972-05-01), Ho et al.
patent: 3990056 (1976-11-01), Luisi et al.
Frohman et al., Metal-Nitride-Oxide-Silicon-Transistor, Proceedings of the IEEE, 8/70, pp. 1218-1219.

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