Ramptime propagation on designs with cycles

Details Ramptime propagation on designs with cycles Ramptime propagation on designs with cycles

2007-07-17

2007-07-17

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

11004309

ABSTRACT:
A method for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.

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Hao Zheng et al. “Modular Verification of Timed Circuits Using Automatic Abstraction,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, No. 9, Sep. 2003, pp. 1138-1153.

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